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msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 msp430fr688x(1), msp430fr588x(1) mixed-signal microcontrollers 1 device overview 1.1 features 1 ? accessible bit-, byte- and word-wise (in pairs) ? embedded microcontroller ? edge-selectable wakeup from lpm on ports ? 16-bit risc architecture up to 16-mhz clock p1, p2, p3, and p4 ? wide supply voltage range (1.8 v to 3.6 v) (1) ? programmable pullup and pulldown on all ports ? optimized ultra-low-power modes ? code security ? active mode: approximately 100 a/mhz ? true random number seed for random ? standby (lpm3 with vlo): 0.4 a (typical) number generation algorithm ? real-time clock (rtc) (lpm3.5): 0.35 a ? enhanced serial communication (typical) (2) ? eusci_a0 and eusci_a1 support: ? shutdown (lpm4.5): 0.02 a (typical) ? uart with automatic baud-rate detection ? ultra-low-power ferroelectric ram (fram) ? irda encode and decode ? up to 128kb of nonvolatile memory ? spi at rates up to 10 mbps ? ultra-low-power writes ? eusci_b0 and eusci_b1 support: ? fast write at 125 ns per word (64kb in 4 ms) ? i 2 c with multiple-slave addressing ? unified memory = program + data + storage in ? spi at rates up to 10 mbps one single space ? hardware uart and i 2 c bootstrap loader ? 10 15 write cycle endurance (bsl) ? radiation resistant and nonmagnetic ? flexible clock system ? intelligent digital peripherals ? fixed-frequency dco with 10 selectable ? 32-bit hardware multiplier (mpy) factory-trimmed frequencies ? three-channel internal direct memory access ? low-power low-frequency internal clock (dma) source (vlo) ? rtc with calendar and alarm functions ? 32-khz crystals (lfxt) ? five 16-bit timers with up to seven ? high-frequency crystals (hfxt) capture/compare registers each ? development tools and software ? 16-bit and 32-bit cyclic redundancy checker ? free professional development environments (crc16, crc32) with energytrace++ ? technology ? high-performance analog ? experimenter and development kits ? extended scan interface (esi) for background ? family members water, heat, and gas volume measurement ? section 3 summarizes the device variants and ? 16-channel analog comparator available packages types ? 12-bit analog-to-digital converter (adc) with ? for complete module descriptions, see the internal reference and sample-and-hold and msp430fr58xx, msp430fr59xx, up to 16 external input channels msp430fr68xx, and msp430fr69xx family ? integrated lcd driver with contrast control for user's guide ( slau367 ) up to 320 segments ? multifunction input/output ports ? all p1 to p10 and pj pins support capacitive touch capability without need for external components (1) minimum supply voltage is restricted by svs levels. (2) rtc is clocked by a 3.7-pf crystal. 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. productfolder sample &buy technical documents tools & software support &community
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 1.2 applications ? water meters ? portable medical meters ? heat meters ? data logging ? heat cost allocators ? see section 7.2.3 for ti designs 1.3 description the msp430 ? ultra-low-power (ulp) fram platform combines uniquely embedded fram and a holistic ultra-low-power system architecture, allowing innovators to increase performance at lowered energy budgets. fram technology combines the speed, flexibility, and endurance of sram with the stability and reliability of flash at much lower power. the msp430 ulp fram portfolio consists of a diverse set of devices that feature fram, the ulp 16-bit msp430 cpu, and intelligent peripherals targeted for various applications. the ulp architecture showcases seven low-power modes, which are optimized to achieve extended battery life in energy- challenged applications. device information (1) part number package body size (2) msp430fr6889pz lqfp (100) 14 mm 14 mm msp430fr6889pn lqfp (80) 12 mm 12 mm msp430fr5889pm lqfp (64) 10 mm 10 mm msp430fr5889rgc vqfn (64) 9 mm 9 mm (1) for the most current part, package, and ordering information, see the package option addendum in section 9 , or see the ti website at www.ti.com . (2) the sizes shown here are approximations. for the package dimensions with tolerances, see the mechanical data in section 9 . 2 device overview copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 1.4 functional block diagram figure 1-1 and figure 1-2 show the functional block diagrams. figure 1-1. functional block diagram ? msp430fr688x, msp430fr688x1 copyright ? 2014 ? 2015, texas instruments incorporated device overview 3 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 rtc rtc rtc _ _ _ a a a comp_e (up to 16 inputs) fram up to 128kb ram 2kb power mgmt ldo svs brownout smclk aclk mdb mab lfxout/hfxout lfxin/ hfxin spy-bi- wire crc32 crc-32- iso-3309 crc16 crc-16- ccitt bus control logic mabmdb mab mdb mclk mpy32 adc12_b (up to 16 std. inputs, up to 8 diff. inputs) clock system cpuxv2 incl. 16 registers jtag interface dma controller 3 channel ref_a voltage reference mpu ip encap tb0 timer_b 7 cc registers (int./ext.) ta0 timer_a 3 cc registers (int./ext.) ta1 timer_a 3 cc registers (int./ext.) rtc_c calendar and counter mode lcd_c (up to 320 seg; static, 2 - 8 mux) extended scan interface eusci_a0eusci_a1 (uart, irda, spi) eusci_b0eusci_b1 (i2c, spi) lpm3.5 domain p1.x/p2.x 2x8 i/o port p5/6 2x8 i/os pc 1x16 i/os i/o port p7/8 2x8 i/os pd 1x16 i/os i/o port p9/10 1x8 i/os pe 1x16 i/os i/o port pj 1x8 i/os i/o ports p3/4 2x8 i/os pb 1x16 i/os i/o ports p1/2 2x8 i/os pa 1x16 i/os p 5 .x/p6.x 2x8 p9.x/p10.x 2x8 pj.x 1x8 p3.x/p4.x 2x8 p 7 .x/p 8 .x 2x8 watchdog ta2 timer_a 2 cc registers (int. only) ta3 timer_a 5 cc registers (int. only) eem (s: 3 + 1) energytrace++ capacitive touch io 0, capacitive touch io 1
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com figure 1-2. functional block diagram ? msp430fr588x, msp430fr588x1 4 device overview copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 rtc rtc _ _ a a comp_e (up to 16 inputs) fram up to 128kb ram 2kb power mgmt ldo svs brownout smclk aclk mdb mab lfxout/hfxout lfxin/ hfxin spy-bi- wire crc32 crc-32- iso-3309 crc16 crc-16- ccitt bus logic control mabmdb mab mdb mclk mpy32 adc12_b (up to 16 std. inputs, up to 8 diff. inputs) clock system cpuxv2 incl. 16 registers jtag interface dma controller 3 channel ref_a voltage reference mpu ip encap tb0 timer_b 7 cc registers (int./ext.) ta0 timer_a 3 cc registers (int./ext.) ta1 timer_a 3 cc registers (int./ext.) rtc_c calendar and counter mode extended scan interface eusci_a0eusci_a1 (uart, irda, spi) eusci_b0eusci_b1 (i2c, spi) lpm3.5 domain p1.x/p2.x 2x8 i/o port p5/6 2x8 i/os pc 1x16 i/os i/o port p7/8 2x8 i/os pd 1x16 i/os i/o port p9/10 1x8 i/os pe 1x16 i/os i/o port pj 1x8 i/os i/o ports p3/4 2x8 i/os pb 1x16 i/os i/o ports p1/2 2x8 i/os pa 1x16 i/os p 5 .x/p6.x 2x8 p9.x/p10.x 2x8 pj.x 1x8 p3.x/p4.x 2x8 p 7 .x/p 8 .x 2x8 watchdog ta2 timer_a 2 cc registers (int. only) ta3 timer_a 5 cc registers (int. only) capacitive touch io 0, 1 capacitive touch io eem (s: 3 + 1) energytrace++
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table of contents 5.11 typical characteristics, current consumption per 1 device overview ......................................... 1 module .............................................. 36 1.1 features .............................................. 1 5.12 thermal packaging characteristics ................ 37 1.2 applications ........................................... 2 5.13 timing and switching characteristics ............... 38 1.3 description ............................................ 2 6 detailed description ................................... 71 1.4 functional block diagram ............................ 3 6.1 overview ............................................ 71 2 revision history ......................................... 6 6.2 cpu ................................................. 71 3 device comparison ..................................... 7 6.3 operating modes .................................... 72 4 terminal configuration and functions .............. 8 6.4 interrupt vector table and signatures .............. 74 4.1 pin diagram ? pz package ? msp430fr688x, msp430fr688x1 ..................................... 8 6.5 bootstrap loader (bsl) ............................. 77 4.2 pin diagram ? pn package ? msp430fr688x, 6.6 jtag operation ..................................... 77 msp430fr688x1 ..................................... 9 6.7 fram ................................................ 78 4.3 pin diagram ? pm or rgc package ? 6.8 ram ................................................. 78 msp430fr588x, msp430fr588x1 ................ 10 6.9 tiny ram ............................................ 78 4.4 signal descriptions .................................. 11 6.10 memory protection unit including ip encapsulation 78 4.5 pin multiplexing ..................................... 27 6.11 peripherals .......................................... 79 4.6 connection of unused pins ......................... 27 6.12 device descriptors (tlv) .......................... 126 5 specifications ........................................... 28 6.13 memory ............................................ 129 5.1 absolute maximum ratings ......................... 28 6.14 identification ........................................ 147 5.2 esd ratings ........................................ 28 7 applications, implementation, and layout ...... 148 5.3 recommended operating conditions ............... 28 7.1 device connection and layout fundamentals .... 148 5.4 active mode supply current into v cc excluding 7.2 peripheral- and interface-specific design external current (havok) ........................... 29 information ......................................... 152 5.5 typical characteristics, active mode supply 8 device and documentation support .............. 158 currents ............................................. 30 8.1 device support ..................................... 158 5.6 low-power mode (lpm0, lpm1) supply currents into v cc excluding external current ................ 30 8.2 documentation support ............................ 161 5.7 low-power mode lpm2, lpm3, lpm4 supply 8.3 trademarks ........................................ 162 currents (into v cc ) excluding external current .... 31 8.4 electrostatic discharge caution ................... 162 5.8 low-power mode with lcd supply currents (into 8.5 export control notice .............................. 162 v cc ) excluding external current .................... 33 8.6 glossary ............................................ 162 5.9 low-power mode lpmx.5 supply currents (into 9 mechanical, packaging, and orderable v cc ) excluding external current .................... 34 information ............................................. 162 5.10 typical characteristics, low-power mode supply currents ............................................. 35 9.1 packaging information ............................. 162 copyright ? 2014 ? 2015, texas instruments incorporated table of contents 5 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 2 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from august 28, 2014 to march 9, 2015 page ? moved t stg to section 5.1 and removed handling ratings table .............................................................. 28 ? added section 5.2 , esd ratings .................................................................................................. 28 ? changed " i lpm3,xt12 " parameter from " includes svs " to " excludes svs " .................................................... 31 ? deleted " ram disabled. " from footnote for i lpm3,vlo . ........................................................................... 31 ? changed note from " low-power mode 3, 12-pf crystal, including svs " to " ...excluding svs " , and changed listed test conditions to exclude svs .................................................................................................... 31 ? deleted " ram disabled. " from footnote for i lpm4 . ............................................................................... 32 ? in the second row of the i vmid parameter, changed the unit from a to na, and converted max value to new unit (from 1.6 a to 1600 na) ...................................................................................................... 67 ? moved " fram access time error " interrupt source and " accteifg " interrupt flag from " system nmi " to " system reset " row ............................................................................................................................ 74 ? added eusci_b1 to list in section 6.11.22.2 ................................................................................... 88 ? switched pxsel0.y and pxsel1.y inputs in figure 6-1 to correct inputs to multiplexers ................................. 90 ? switched p1sel0.x and p1sel1.x inputs in p1.0 to p1.3 schematic to show correct inputs to multiplexers .......... 92 ? switched p2sel0.x and p2sel1.x inputs in p2.4 to p2.7 schematic to show correct inputs to multiplexers .......... 96 ? switched p6sel0.x and p6sel1.x inputs in p6.0 to p6.7 schematic to show correct inputs to multiplexers ........ 104 ? switched p8sel0.x and p8sel1.x inputs in p8.4 to p8.7 schematic to show correct inputs to multiplexers ........ 111 ? switched p9sel0.x and p9sel1.x inputs in p9.0 to p9.3 schematic to show correct inputs to multiplexers ........ 113 ? switched p9sel0.x and p9sel1.x inputs in p9.4 to p9.7 schematic to show correct inputs to multiplexers ........ 115 ? switched pjsel0.4 and pjsel1.4 inputs in pj.4 schematic to show correct inputs to multiplexers .................. 118 ? switched pjsel0.5 and pjsel1.5 inputs in pj.5 schematic to show correct inputs to multiplexers .................. 119 ? switched pjsel0.6 and pjsel1.6 inputs in pj.6 schematic to show correct inputs to multiplexers .................. 121 ? switched pjsel0.7 and pjsel1.7 inputs in pj.7 schematic to show correct inputs to multiplexers .................. 122 ? switched p1sel0.x and p1sel1.x inputs in section 6.11.23.20 schematic ............................................. 124 ? changed figure 8-1 : corrected " esi " label. added note. .................................................................... 160 6 revision history copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 3 device comparison table 3-1 and table 3-2 summarize the available family members. table 3-1. device comparison (with uart bsl) (1) (2) eusci fram sram clock timer_a timer_b package device aes adc12_b lcd_c i/o (kb) (kb) system (3) (4) type a (5) b (6) dco 3, 3 (7) 12 ext 240 seg 63 80 pn msp430fr6889 128 2 hfxt 7 2 2 no 2, 5 (8) 16 ext 320 seg 83 100 pz lfxt dco 3, 3 (7) 12 ext 240 seg 63 80 pn msp430fr6888 96 2 hfxt 7 2 2 no 2, 5 (8) 16 ext 320 seg 83 100 pz lfxt dco 3, 3 (7) 12 ext 240 seg 63 80 pn msp430fr6887 64 2 hfxt 7 2 2 no 2, 5 (8) 16 ext 320 seg 83 100 pz lfxt dco 3, 3 (7) 64 pm msp430fr5889 128 2 hfxt 7 2 2 no 12 ext n/a 48 2, 5 (8) 64 rgc lfxt dco 3, 3 (7) 64 pm msp430fr5888 96 2 hfxt 7 2 2 no 12 ext n/a 48 2, 5 (8) 64 rgc lfxt dco 3, 3 (7) 64 pm msp430fr5887 64 2 hfxt 7 2 2 no 12 ext n/a 48 2, 5 (8) 64 rgc lfxt (1) for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti web site at www.ti.com . (2) package drawings, standard packing quantities, thermal data, symbolization, and pcb design guidelines are available at www.ti.com/package . (3) each number in the sequence represents an instantiation of timer_a with its associated number of capture compare registers and pwm output generators available. for example, a number sequence of 3, 5 would represent two instantiations of timer_a, the first instantiation having 3 and the second instantiation having 5 capture compare registers and pwm output generators, respectively. (4) each number in the sequence represents an instantiation of timer_b with its associated number of capture compare registers and pwm output generators available. for example, a number sequence of 3, 5 would represent two instantiations of timer_b, the first instantiation having 3 and the second instantiation having 5 capture compare registers and pwm output generators, respectively. (5) eusci_a supports uart with automatic baud-rate detection, irda encode and decode, and spi. (6) eusci_b supports i 2 c with multiple slave addresses and spi. (7) timer_a ta0 and ta1 provide internal and external capture/compare inputs and internal and external pwm outputs. (8) timer_a ta2 and ta3 provide only internal capture/compare inputs and only internal pwm outputs (if any). table 3-2. device comparison (with i 2 c bsl) (1) (2) eusci fram sram clock timer_a timer_b package device aes adc12_b lcd_c i/o (kb) (kb) system (3) (4) type a (5) b (6) dco 3, 3 (7) 12 ext 240 seg 63 80 pn msp430fr68891 128 2 hfxt 7 2 2 no 2, 5 (8) 16 ext 320 seg 83 100 pz lfxt dco 3, 3 (7) 64 pm msp430fr58891 128 2 hfxt 7 2 2 no 12 ext n/a 48 2, 5 (8) 64 rgc lfxt (1) for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti web site at www.ti.com . (2) package drawings, standard packing quantities, thermal data, symbolization, and pcb design guidelines are available at www.ti.com/package . (3) each number in the sequence represents an instantiation of timer_a with its associated number of capture compare registers and pwm output generators available. for example, a number sequence of 3, 5 would represent two instantiations of timer_a, the first instantiation having 3 and the second instantiation having 5 capture compare registers and pwm output generators, respectively. (4) each number in the sequence represents an instantiation of timer_b with its associated number of capture compare registers and pwm output generators available. for example, a number sequence of 3, 5 would represent two instantiations of timer_b, the first instantiation having 3 and the second instantiation having 5 capture compare registers and pwm output generators, respectively. (5) eusci_a supports uart with automatic baud-rate detection, irda encode and decode, and spi. (6) eusci_b supports i 2 c with multiple slave addresses and spi. (7) timer_a ta0 and ta1 provide internal and external capture/compare inputs and internal and external pwm outputs. (8) timer_a ta2 and ta3 provide only internal capture/compare inputs and only internal pwm outputs (if any). copyright ? 2014 ? 2015, texas instruments incorporated device comparison 7 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 4 terminal configuration and functions 4.1 pin diagram ? pz package ? msp430fr688x, msp430fr688x1 figure 4-1 shows the 100-pin pz package pin assignments. on devices with uart bsl: p2.0: bsltx; p2.1: bslrx on devices with i 2 c bsl: p1.6: bslsda; p1.7: bslscl figure 4-1. 100-pin pz package (top view) 8 terminal configuration and functions copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 1 p4.3/uca0somi/uca0rxd/ucb1ste 2 p1.4/ucb0clk/uca0ste/ta1.0/s1 3 p1.5/ucb0ste/uca0clk/ta0.0/s0 4 p1.6/ucb0simo/ucb0sda/ta0.1 5 p1.7/ucb0somi/ucb0scl/ta0.2 6 r33/lcdcap 7 p6.0/r23 8 p6.1/r13/lcdref 9 p6.2/cout/r03 10 p6.3/com0 11 p6.4/tb0.0/com1 12 p6.5/tb0.1/com2 13 p6.6/tb0.2/com3 14 p2.4/tb0.3/com4/s43 15 p2.5/tb0.4/com5/s42 16 p2.6/tb0.5/esic1out/com6/s41 17 p2.7/tb0.6/ com7/s40 esic2out/ 18 p10.2/ta1.0/smclk/s39 19 p5.0/ta1.1/mclk/s38 20 p5.1/ta1.2/s37 21 p5.2/ta1.0/ta1clk/aclk/s36 22 p5.3/ucb1ste/s35 23 p3.0/ucb1clk/s34 24 p3.1/ucb1simo/ucb1sda/s33 25 p3.2/ucb1somi/ucb1scl/s32 26 dvss1 27 dvcc1 28 test/sbwtck 29 rst/nmi/sbwtdio 30 pj.0/tdo/tb0outh/smclk/srscg1 31 pj.1/tdi/tclk/mclk/srscg0 32 pj.2/tms/aclk/sroscoff 33 pj.3/tck/cout/srcpuoff 34 p6.7/ta0clk/s31 35 p7.5/ta0.2/s30 36 p7.6/ta0.1/s29 37 p10.1/ta0.0/s28 38 p7.7/ta1.2/tb0outh/s27 39 p3.3/ta1.1/tb0clk/s26 40 p3.4/uca1simo/uca1txd/tb0.0/s25 41 p3.5/uca1somi/uca1rxd/tb0.1/s24 42 p3.6/uca1clk/tb0.2/s23 43 p3.7/uca1ste/tb0.3/s22 44 p8.0/rtcclk/s21 45 p8.1/dmae0/s20 46 p8.2/s19 47 p8.3/mclk/s18 48 p2.3/uca0ste/tb0outh 49 p2.2/uca0clk/tb0.4/rtcclk 50 p2.1/uca0somi/uca0rxd/tb0.5/dmae0 51 p2.0/uca0simo/uca0txd/tb0.6/tb0clk 52 p7.0/ta0clk/s17 53 p7.1/ta0.0/s16 54 p7.2/ta0.1/s15 55 p7.3/ta0.2/s14 56 p7.4/smclk/s13 57 dvss2 58 dvcc2 59 p8.4/a7/c7 60 p8.5/a6/c6 61 p8.6/a5/c5 62 p8.7/a4/c4 63 p1.3/ta1.2 /a3/c3 /esitest4 64 p1.2/ta1.1/ta0clk/cout/a2/c2 65 p1.1/ta0.2/ta1clk/cout/a1/c1/vref+/veref+ 66 p1.0/ta0.1/dmae0/rtcclk/a0/c0/vref-/veref- 67 p9.0/esich0/esitest0/a8/c8 68 p9.1/esich1/esitest1/a9/c9 69 p9.2/esich2/esitest2/a10/c10 70 p9.3/esich3/esitest3/a11/c11 71 p9.4/esici0/a12/c12 72 p9.5/esici1/a13/c13 73 p9.6/esici2/a14/c14 74 p9.7/esici3/a15/c15 75 esidvcc 76 esidvss 77 esici 78 esicom 79 avcc1 80 avss3 81 pj.7/hfxout 82 pj.6/hfxin 83 avss1 84 pj.4/lfxin 85 pj.5/lfxout 86 avss2 87 p5.4/uca1simo/uca1txd/s12 88 p5.5/uca1somi/uca1rxd/s11 89 p5.6/uca1clk/s10 90 p5.7/uca1ste/tb0clk/s9 91 p4.4/ucb1ste/ta1clk/s8 92 p4.5/ucb1clk/ta1.0/s7 93 p4.6/ucb1simo/ucb1sda/ta1.1/s6 94 p4.7/ucb1somi/ucb1scl/ta1.2/s5 95 p10.0/smclk/s4 96 p4.0/ucb1simo/ucb1sda/mclk/s3 97 p4.1/ucb1somi/ucb1scl/aclk/s2 98 dvss3 99 dvcc3 100 p4.2/uca0simo/uca0txd/ucb1clk
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 4.2 pin diagram ? pn package ? msp430fr688x, msp430fr688x1 figure 4-2 shows the 80-pin pn package pin assignments. on devices with uart bsl: p2.0: bsltx; p2.1: bslrx on devices with i 2 c bsl: p1.6: bslsda; p1.7: bslscl figure 4-2. 80-pin pn package (top view) copyright ? 2014 ? 2015, texas instruments incorporated terminal configuration and functions 9 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 1 p4.3/uca0somi/uca0rxd/ucb1ste 2 p1.4/ucb0clk/uca0ste/ta1.0/s3 3 p1.5/ucb0ste/uca0clk/ta0.0/s2 4 p1.6/ /ta0.1/s1 ucb0simo/ucb0sda 5 p1.7/ /ta0.2/s0 ucb0somi/ucb0scl 6 r33/lcdcap 7 p6.0/r23 8 p6.1/r13/lcdref 9 p6.2/cout/r03 10 p6.3/com0 11 p6.4/tb0.0/com1/s36 12 p6.5/tb0.1/com2/s35 13 p6.6/tb0.2/com3/s34 14 p2.4/tb0.3/com4/s33 15 p2.5/tb0.4/com5/s32 16 p2.6/tb0.5/esic1out/com6/s31 17 p2.7/tb0.6/ com7/s30 esic2out/ 18 p3.0/ucb1clk/s29 19 p3.1/ /s28 ucb1simo/ucb1sda 20 p3.2/ /s27 ucb1somi/ucb1scl 21 dvss1 22 dvcc1 23 test/sbwtck 24 rst/nmi/sbwtdio 25 pj.0/tdo/tb0outh/smclk/srscg1 26 pj.1/tdi/tclk/mclk/srscg0 27 pj.2/tms/aclk/sroscoff 28 pj.3/tck/cout/srcpuoff 29 p6.7/ta0clk/s26 30 p7.5/ta0.2/s25 31 p7.6/ta0.1/s24 32 p7.7/ta1.2/tb0outh/s23 33 p3.3/ta1.1/tb0clk/s22 34 p3.4/uca1simo/uca1txd/tb0.0/s21 35 p3.5/uca1somi/uca1rxd/tb0.1/s20 36 p3.6/uca1clk/tb0.2/s19 37 p3.7/uca1ste/tb0.3/s18 38 p2.3/uca0ste/tb0outh/s17 39 p2.2/uca0clk/tb0.4/rtcclk/s16 40 p2.1/uca0somi/uca0rxd/tb0.5/dmae0/s15 41 p2.0/uca0simo/uca0txd/tb0.6/tb0clk/s14 42 p7.0/ta0clk/s13 43 p7.1/ta0.0/s12 44 p7.2/ta0.1/s11 45 p7.3/ta0.2/s10 46 dvss2 47 dvcc2 48 p1.3/ta1.2 /a3/c3 /esitest4 49 p1.2/ta1.1/ta0clk/cout/a2/c2 50 p1.1/ta0.2/ta1clk/cout/a1/c1/vref+/veref+ 51 p1.0/ta0.1/dmae0/rtcclk/a0/c0/vref-/veref- 52 p9.0/esich0/esitest0/a8/c8 53 p9.1/esich1/esitest1/a9/c9 54 p9.2/esich2/esitest2/a10/c10 55 p9.3/esich3/esitest3/a11/c11 56 p9.4/esici0/a12/c12 57 p9.5/esici1/a13/c13 58 p9.6/esici2/a14/c14 59 p9.7/esici3/a15/c15 60 esidvcc 61 esidvss 62 esici 63 esicom 64 avcc1 65 avss3 66 pj.7/hfxout 67 pj.6/hfxin 68 avss1 69 pj.4/lfxin 70 pj.5/lfxout 71 avss2 72 p4.4/ucb1ste/ta1clk/s9 73 p4.5/ucb1clk/ta1.0/s8 74 p4.6/ /ta1.1/s7 ucb1simo/ucb1sda 75 p4.7/ /ta1.2/s6 ucb1somi/ucb1scl 76 p4.0/ mclk/s5 ucb1simo/ucb1sda/ 77 p4.1/ aclk/s4 ucb1somi/ucb1scl/ 78 dvss3 79 dvcc3 80 p4.2/uca0simo/uca0txd/ucb1clk
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 4.3 pin diagram ? pm or rgc package ? msp430fr588x, msp430fr588x1 figure 4-3 shows the 64-pin pm or rgc package pin assignments. on devices with uart bsl: p2.0: bsltx; p2.1: bslrx on devices with i 2 c bsl: p1.6: bslsda; p1.7: bslscl figure 4-3. 64-pin pm or rgc package (top view) 10 terminal configuration and functions copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 1 p4.3/uca0somi/uca0rxd/ucb1ste 2 p1.4/ucb0clk/uca0ste/ta1.0 3 p1.5/ucb0ste/uca0clk/ta0.0 4 p1.6/ ta0.1 ucb0simo/ucb0sda/ 5 p1.7/ ta0.2 ucb0somi/ucb0scl/ 6 p2.4/tb0.3 7 p2.5/tb0.4 8 p2.6/tb0.5/esic1out 9 p2.7/tb0.6/esic2out 10 p5.0/ta1.1/mclk 11 p5.1/ta1.2 12 p5.2/ta1.0/ta1clk/aclk 13 p5.3/ucb1ste 14 p3.0/ucb1clk 15 p3.1/ucb1simo/ucb1sda 16 p3.2/ucb1somi/ucb1scl 17 dvss1 18 dvcc1 19 test/sbwtck 20 rst/nmi/sbwtdio 21 pj.0/tdo/tb0outh/smclk/srscg1 22 pj.1/tdi/tclk/mclk/srscg0 23 pj.2/tms/aclk/sroscoff 24 pj.3/tck/cout/srcpuoff 25 p3.3/ta1.1/tb0clk 26 p3.4/uca1simo/uca1txd/tb0.0 27 p3.5/uca1somi/uca1rxd/tb0.1 28 p3.6/uca1clk/tb0.2 29 p3.7/uca1ste/tb0.3 30 p2.3/uca0ste/tb0outh 31 p2.2/uca0clk/tb0.4/rtcclk 32 p2.1/uca0somi/uca0rxd/tb0.5/dmae0 33 p2.0/uca0simo/uca0txd/tb0.6/tb0clk 34 dvss2 35 dvcc2 36 p1.3/ta1.2 /a3/c3 /esitest4 37 p1.2/ta1.1/ta0clk/cout/a2/c2 38 p1.1/ta0.2/ta1clk/cout/a1/c1/vref+/veref+ 39 p1.0/ta0.1/dmae0/rtcclk/a0/c0/vref-/veref- 40 p9.0/esich0/esitest0/a8/c8 41 p9.1/esich1/esitest1/a9/c9 42 p9.2/esich2/esitest2/a10/c10 43 p9.3/esich3/esitest3/a11/c11 44 p9.4/esici0/a12/c12 45 p9.5/esici1/a13/c13 46 p9.6/esici2/a14/c14 47 p9.7/esici3/a15/c15 48 esidvcc 49 esidvss 50 esici 51 esicom 52 avcc1 53 avss3 54 pj.7/hfxout 55 pj.6/hfxin 56 avss1 57 pj.4/lfxin 58 pj.5/lfxout 59 avss2 60 p4.0/ucb1simo/ucb1sda/mclk 61 p4.1/ aclk ucb1somi/ucb1scl/ 62 dvss3 63 dvcc3 64 p4.2/uca0simo/uca0txd/ucb1clk
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 4.4 signal descriptions table 4-1 and table 4-2 describe the device signals. table 4-1. msp430fr688x, msp430fr688x1 signal descriptions terminal pz pn description name no. seg. no. seg. general-purpose digital i/o usci_a0: slave out, master in (spi mode) p4.3/uca0somi/uca0rxd/ 1 1 ucb1ste usci_a0: receive data (uart mode) usci_b1: slave transmit enable (spi mode) general-purpose digital i/o usci_b0: clock signal input (spi slave mode), clock signal output (spi master mode) p1.4/ucb0clk/uca0ste/ 2 s1 2 s3 ta1.0/sx usci_a0: slave transmit enable (spi mode) timer_a ta1 ccr0 capture: cci0a input, compare: out0 output lcd segment output (segment number is package specific) general-purpose digital i/o usci_b0: slave transmit enable (spi mode) p1.5/ucb0ste/ usci_a0: clock signal input (spi slave mode), clock signal output (spi 3 s0 3 s2 uca0clk/ta0.0/sx master mode) timer_a ta0 ccr0 capture: cci0a input, compare: out0 output lcd segment output (segment number is package specific) general-purpose digital i/o usci_b0: slave in, master out (spi mode) usci_b0: i 2 c data (i 2 c mode) p1.6/ucb0simo/ucb0sda/ 4 4 s1 ta0.1/sx bsl data (i 2 c bsl) timer_a ta0 ccr1 capture: cci1a input, compare: out1 output lcd segment output (segment number is package specific) general-purpose digital i/o usci_b0: slave out, master in (spi mode) usci_b0: i 2 c clock (i 2 c mode) p1.7/ucb0somi/ucb0scl/ 5 5 s0 ta0.2/sx bsl clock (i 2 c bsl) timer_a ta0 ccr2 capture: cci2a input, compare: out2 output lcd segment output (segment number is package specific) input/output port of most positive analog lcd voltage (v1) r33/lcdcap 6 6 lcd capacitor connection general-purpose digital i/o p6.0/r23 7 7 input/output port of second most positive analog lcd voltage (v2) general-purpose digital i/o p6.1/r13/lcdref 8 8 input/output port of third most positive analog lcd voltage (v3 or v4) external reference voltage input for regulated lcd voltage general-purpose digital i/o p6.2/cout/r03 9 9 comparator output input/output port of lowest analog lcd voltage (v5) copyright ? 2014 ? 2015, texas instruments incorporated terminal configuration and functions 11 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com table 4-1. msp430fr688x, msp430fr688x1 signal descriptions (continued) terminal pz pn description name no. seg. no. seg. general-purpose digital i/o p6.3/com0 10 10 lcd common output com0 for lcd backplane general-purpose digital i/o timer_b tb0 ccr0 capture: cci0b input, compare: out0 output p6.4/tb0.0/com1/sx 11 11 s36 lcd common output com1 for lcd backplane lcd segment output (segment number is package specific) general-purpose digital i/o timer_b tb0 ccr1 capture: cci1a input, compare: out1 output p6.5/tb0.1/com2/sx 12 12 s35 lcd common output com2 for lcd backplane lcd segment output (segment number is package specific) general-purpose digital i/o timer_b tb0 ccr2 capture: cci2a input, compare: out2 output p6.6/tb0.2/com3/sx 13 13 s34 lcd common output com3 for lcd backplane lcd segment output (segment number is package specific) general-purpose digital i/o timer_b tb0 ccr3 capture: cci3a input, compare: out3 output p2.4/tb0.3/com4/sx 14 s43 14 s33 lcd common output com4 for lcd backplane lcd segment output (segment number is package specific) general-purpose digital i/o timer_b tb0 ccr4 capture: cci4a input, compare: out4 output p2.5/tb0.4/com5/sx 15 s42 15 s32 lcd common output com5 for lcd backplane lcd segment output (segment number is package specific) general-purpose digital i/o timer_b tb0 ccr5 capture: cci5a input, compare: out5 output p2.6/tb0.5/ esic1out/ 16 s41 16 s31 esi comparator 1 output com6/sx lcd common output com6 for lcd backplane lcd segment output (segment number is package specific) general-purpose digital i/o timer_b tb0 ccr6 capture: cci6a input, compare: out6 output p2.7/tb0.6/ esic2out/ 17 s40 17 s30 esi comparator 2 output com7/sx lcd common output com7 for lcd backplane lcd segment output (segment number is package specific) general-purpose digital i/o timer_a ta1 ccr0 capture: cci0b input, compare: out0 output p10.2/ta1.0/smclk/sx 18 s39 smclk output lcd segment output (segment number is package specific) general-purpose digital i/o timer_a ta1 ccr1 capture: cci1a input, compare: out1 output p5.0/ta1.1/mclk/sx 19 s38 mclk output lcd segment output (segment number is package specific) 12 terminal configuration and functions copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 4-1. msp430fr688x, msp430fr688x1 signal descriptions (continued) terminal pz pn description name no. seg. no. seg. general-purpose digital i/o p5.1/ta1.2/sx 20 s37 timer_a ta1 ccr2 capture: cci2a input, compare: out2 output lcd segment output (segment number is package specific) general-purpose digital i/o timer_a ta1 ccr0 capture: cci0b input, compare: out0 output p5.2/ta1.0/ta1clk/aclk/sx 21 s36 timer_a ta1 clock signal ta0clk input aclk output (divided by 1, 2, 4, or 8) lcd segment output (segment number is package specific) general-purpose digital i/o p5.3/ucb1ste/sx 22 s35 usci_b1: slave transmit enable (spi mode) lcd segment output (segment number is package specific) general-purpose digital i/o usci_b1: clock signal input (spi slave mode), clock signal output (spi p3.0/ucb1clk/sx 23 s34 18 s29 master mode) lcd segment output (segment number is package specific) general-purpose digital i/o usci_b1: slave in, master out (spi mode) p3.1/ucb1simo/ucb1sda/ 24 s33 19 s28 sx usci_b1: i 2 c data (i 2 c mode) lcd segment output (segment number is package specific) general-purpose digital i/o usci_b1: slave out, master in (spi mode) p3.2/ucb1somi/ucb1scl/ 25 s32 20 s27 sx usci_b1: i 2 c clock (i 2 c mode) lcd segment output (segment number is package specific) dvss1 26 21 digital ground supply dvcc1 27 22 digital power supply test mode pin - select digital i/o on jtag pins test/sbwtck 28 23 spy-bi-wire input clock reset input active low rst/nmi/sbwtdio 29 24 nonmaskable interrupt input spy-bi-wire data input/output general-purpose digital i/o test data output port pj.0/tdo/tb0outh/ 30 25 switch all pwm outputs high impedance input - timer_b tb0 smclk/srscg1 smclk output low-power debug: cpu status register scg1 general-purpose digital i/o test data input or test clock input pj.1/tdi/tclk/mclk/ 31 26 srscg0 mclk output low-power debug: cpu status register scg0 copyright ? 2014 ? 2015, texas instruments incorporated terminal configuration and functions 13 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com table 4-1. msp430fr688x, msp430fr688x1 signal descriptions (continued) terminal pz pn description name no. seg. no. seg. general-purpose digital i/o test mode select pj.2/tms/aclk/sroscoff 32 27 aclk output (divided by 1, 2, 4, or 8) low-power debug: cpu status register oscoff general-purpose digital i/o test clock pj.3/tck/cout/srcpuoff 33 28 comparator output low-power debug: cpu status register cpuoff general-purpose digital i/o p6.7/ta0clk/sx 34 s31 29 s26 timer_a ta0 clock signal ta0clk input lcd segment output (segment number is package specific) general-purpose digital i/o p7.5/ta0.2/sx 35 s30 30 s25 timer_a ta0 ccr2 capture: cci2a input, compare: out2 output lcd segment output (segment number is package specific) general-purpose digital i/o p7.6/ta0.1/sx 36 s29 31 s24 timer_a ta0 ccr1 capture: cci1a input, compare: out1 output lcd segment output (segment number is package specific) general-purpose digital i/o p10.1/ta0.0/sx 37 s28 timer_a ta0 ccr0 capture: cci0b input, compare: out0 output lcd segment output (segment number is package specific) general-purpose digital i/o timer_a ta1 ccr2 capture: cci2a input, compare: out2 output p7.7/ta1.2/tb0outh/sx 38 s27 32 s23 switch all pwm outputs high impedance input - timer_b tb0 lcd segment output (segment number is package specific) general-purpose digital i/o timer_a ta1 ccr1 capture: cci1a input, compare: out1 output p3.3/ta1.1/tb0clk/sx 39 s26 33 s22 timer_b tb0 clock signal tb0clk input lcd segment output (segment number is package specific) general-purpose digital i/o usci_a1: slave in, master out (spi mode) p3.4/uca1simo/uca1txd/ 40 s25 34 s21 usci_a1: transmit data (uart mode) tb0.0/sx timer_b tb0 ccr0 capture: cci0a input, compare: out0 output lcd segment output (segment number is package specific) general-purpose digital i/o usci_a1: slave out, master in (spi mode) p3.5/uca1somi/uca1rxd/ 41 s24 35 s20 usci_a1: receive data (uart mode) tb0.1/sx timer_b tb0 ccr1 capture: cci1a input, compare: out1 output lcd segment output (segment number is package specific) 14 terminal configuration and functions copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 4-1. msp430fr688x, msp430fr688x1 signal descriptions (continued) terminal pz pn description name no. seg. no. seg. general-purpose digital i/o usci_a1: clock signal input (spi slave mode), clock signal output (spi master mode) p3.6/uca1clk/tb0.2/sx 42 s23 36 s19 timer_b tb0 ccr2 capture: cci2a input, compare: out2 output lcd segment output (segment number is package specific) general-purpose digital i/o usci_a1: slave transmit enable (spi mode) p3.7/uca1ste/tb0.3/sx 43 s22 37 s18 timer_b tb0 ccr3 capture: cci3b input, compare: out3 output lcd segment output (segment number is package specific) general-purpose digital i/o p8.0/rtcclk/sx 44 s21 rtc clock output for calibration lcd segment output (segment number is package specific) general-purpose digital i/o p8.1/dmae0/sx 45 s20 dma external trigger input lcd segment output (segment number is package specific) general-purpose digital i/o p8.2/sx 46 s19 lcd segment output (segment number is package specific) general-purpose digital i/o p8.3/mclk/sx 47 s18 mclk output lcd segment output (segment number is package specific) general-purpose digital i/o usci_a0: slave transmit enable (spi mode) p2.3/uca0ste/tb0outh/sx 48 38 s17 switch all pwm outputs high impedance input - timer_b tb0 lcd segment output (segment number is package specific) general-purpose digital i/o usci_a0: clock signal input (spi slave mode), clock signal output (spi master mode) p2.2/uca0clk/tb0.4/ 49 39 s16 rtcclk/sx timer_b tb0 ccr4 capture: cci4b input, compare: out4 output rtc clock output for calibration lcd segment output (segment number is package specific) general-purpose digital i/o usci_a0: slave out, master in (spi mode) usci_a0: receive data (uart mode) p2.1/uca0somi/uca0rxd/ 50 40 s15 bsl receive (uart bsl) tb0.5/dmae0/sx timer_b tb0 ccr5 capture: cci5b input, compare: out5 output dma external trigger input lcd segment output (segment number is package specific) copyright ? 2014 ? 2015, texas instruments incorporated terminal configuration and functions 15 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com table 4-1. msp430fr688x, msp430fr688x1 signal descriptions (continued) terminal pz pn description name no. seg. no. seg. general-purpose digital i/o usci_a0: slave in, master out (spi mode) usci_a0: transmit data (uart mode) p2.0/uca0simo/uca0txd/ 51 41 s14 bsl transmit (uart bsl) tb0.6/tb0clk/sx timer_b tb0 ccr6 capture: cci6b input, compare: out6 output timer_b tb0 clock signal tb0clk input lcd segment output (segment number is package specific) general-purpose digital i/o p7.0/ta0clk/sx 52 s17 42 s13 timer_a ta0 clock signal ta0clk input lcd segment output (segment number is package specific) general-purpose digital i/o p7.1/ta0.0/sx 53 s16 43 s12 timer_a ta0 ccr0 capture: cci0b input, compare: out0 output lcd segment output (segment number is package specific) general-purpose digital i/o p7.2/ta0.1/sx 54 s15 44 s11 timer_a ta0 ccr1 capture: cci1a input, compare: out1 output lcd segment output (segment number is package specific) general-purpose digital i/o p7.3/ta0.2/sx 55 s14 45 s10 timer_a ta0 ccr2 capture: cci2a input, compare: out2 output lcd segment output (segment number is package specific) general-purpose digital i/o p7.4/smclk/sx 56 s13 smclk output lcd segment output (segment number is package specific) dvss2 57 46 digital ground supply dvcc2 58 47 digital power supply general-purpose digital i/o p8.4/a7/c7 59 analog input a7 comparator input c7 general-purpose digital i/o p8.5/a6/c6 60 analog input a6 comparator input c6 general-purpose digital i/o p8.6/a5/c5 61 analog input a5 comparator input c5 general-purpose digital i/o p8.7/a4/c4 62 analog input a4 comparator input c4 general-purpose digital i/o esi test signal 4 p1.3/ esitest4/ta1.2/a3/c3 63 48 timer_a ta1 ccr2 capture: cci2a input, compare: out2 output analog input a3 comparator input c3 16 terminal configuration and functions copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 4-1. msp430fr688x, msp430fr688x1 signal descriptions (continued) terminal pz pn description name no. seg. no. seg. general-purpose digital i/o timer_a ta1 ccr1 capture: cci1a input, compare: out1 output timer_a ta0 clock signal ta0clk input p1.2/ta1.1/ta0clk/ 64 49 cout/a2/c2 comparator output analog input a2 comparator input c2 general-purpose digital i/o timer_a ta0 ccr2 capture: cci2a input, compare: out2 output timer_a ta1 clock signal ta1clk input comparator output p1.1/ta0.2/ta1clk/ 65 50 cout/a1/c1/vref+/veref+ analog input a1 comparator input c1 output of positive reference voltage input for an external positive reference voltage to the adc general-purpose digital i/o timer_a ta0 ccr1 capture: cci1a input, compare: out1 output dma external trigger input p1.0/ta0.1/dmae0/ rtc clock output for calibration rtcclk/a0/c0/ vref- 66 51 analog input a0 /veref- comparator input c0 output of negative reference voltage input for an external negative reference voltage to the adc general-purpose digital i/o esi channel 0 sensor excitation output and signal input p9.0/ esich0/esitest0/ 67 52 esi test signal 0 a8/c8 analog input a8 comparator input c8 general-purpose digital i/o esi channel 1 sensor excitation output and signal input p9.1/ esich1/esitest1/ 68 53 esi test signal 1 a9/c9 analog input a9 comparator input c9 general-purpose digital i/o esi channel 2 sensor excitation output and signal input p9.2/ esich2/esitest2/ 69 54 a10/c10 esi test signal 2 analog input a10; comparator input c10 general-purpose digital i/o esi channel 3 sensor excitation output and signal input p9.3/ esich3/esitest3/ 70 55 esi test signal 3 a11/c11 analog input a11 comparator input c11 copyright ? 2014 ? 2015, texas instruments incorporated terminal configuration and functions 17 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com table 4-1. msp430fr688x, msp430fr688x1 signal descriptions (continued) terminal pz pn description name no. seg. no. seg. general-purpose digital i/o esi channel 0 signal input to comparator p9.4/ esici0/a12/c12 71 56 analog input a12 comparator input c12 general-purpose digital i/o esi channel 1 signal input to comparator p9.5/ esici1/a13/c13 72 57 analog input a13 comparator input c13 general-purpose digital i/o esi channel 2 signal input to comparator p9.6/ esici2/a14/c14 73 58 analog input a14 comparator input c14 general-purpose digital i/o esi channel 3 signal input to comparator p9.7/ esici3/a15/c15 74 59 analog input a15 comparator input c15 esidvcc 75 60 esi power supply esidvss 76 61 esi ground supply esici 77 62 esi scan if input to comparator esicom 78 63 esi common termination for scan if sensors avcc1 79 64 analog power supply avss3 80 65 analog ground supply general-purpose digital i/o pj.7/hfxout 81 66 output terminal of crystal oscillator xt2 general-purpose digital i/o pj.6/hfxin 82 67 input terminal for crystal oscillator xt2 avss1 83 68 analog ground supply general-purpose digital i/o pj.4/lfxin 84 69 input terminal for crystal oscillator xt1 general-purpose digital i/o pj.5/lfxout 85 70 output terminal of crystal oscillator xt1 avss2 86 71 analog ground supply general-purpose digital i/o usci_a1: slave in, master out (spi mode) p5.4/uca1simo/uca1txd/sx 87 s12 usci_a1: transmit data (uart mode) lcd segment output (segment number is package specific) general-purpose digital i/o usci_a1: slave out, master in (spi mode) p5.5/uca1somi/uca1rxd/ 88 s11 sx usci_a1: receive data (uart mode) lcd segment output (segment number is package specific) 18 terminal configuration and functions copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 4-1. msp430fr688x, msp430fr688x1 signal descriptions (continued) terminal pz pn description name no. seg. no. seg. general-purpose digital i/o usci_a1: clock signal input (spi slave mode), clock signal output (spi p5.6/uca1clk/sx 89 s10 master mode) lcd segment output (segment number is package specific) general-purpose digital i/o usci_a1: slave transmit enable (spi mode) p5.7/uca1ste/tb0clk/sx 90 s9 timer_b tb0 clock signal tb0clk input lcd segment output (segment number is package specific) general-purpose digital i/o usci_b1: slave transmit enable (spi mode) p4.4/ucb1ste/ta1clk/sx 91 s8 72 s9 timer_a ta1 clock signal ta1clk input lcd segment output (segment number is package specific) general-purpose digital i/o usci_b1: clock signal input (spi slave mode), clock signal output (spi master mode) p4.5/ucb1clk/ta1.0/sx 92 s7 73 s8 timer_a ta1 ccr0 capture: cci0a input, compare: out0 output lcd segment output (segment number is package specific) general-purpose digital i/o usci_b1: slave in, master out (spi mode) p4.6/ucb1simo/ucb1sda/ 93 s6 74 s7 usci_b1: i 2 c data (i 2 c mode) ta1.1/sx timer_a ta1 ccr1 capture: cci1a input, compare: out1 output lcd segment output (segment number is package specific) general-purpose digital i/o usci_b1: slave out, master in (spi mode) p4.7/ucb1somi/ucb1scl/ 94 s5 75 s6 usci_b1: i 2 c clock (i 2 c mode) ta1.2/sx timer_a ta1 ccr2 capture: cci2a input, compare: out2 output lcd segment output (segment number is package specific) general-purpose digital i/o p10.0/smclk/sx 95 s4 smclk output lcd segment output (segment number is package specific) general-purpose digital i/o usci_b1: slave in, master out (spi mode) p4.0/ucb1simo/ucb1sda/ 96 s3 76 s5 usci_b1: i 2 c data (i 2 c mode) mclk/sx mclk output lcd segment output (segment number is package specific) general-purpose digital i/o usci_b1: slave out, master in (spi mode) p4.1/ucb1somi/ucb1scl/ 97 s2 77 s4 usci_b1: i 2 c clock (i 2 c mode) aclk/sx aclk output (divided by 1, 2, 4, or 8) lcd segment output (segment number is package specific) dvss3 98 78 digital ground supply dvcc3 99 79 digital power supply copyright ? 2014 ? 2015, texas instruments incorporated terminal configuration and functions 19 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com table 4-1. msp430fr688x, msp430fr688x1 signal descriptions (continued) terminal pz pn description name no. seg. no. seg. general-purpose digital i/o usci_a0: slave in, master out (spi mode) p4.2/uca0simo/uca0txd/ 100 80 usci_a0: transmit data (uart mode) ucb1clk usci_b1: clock signal input (spi slave mode), clock signal output (spi master mode) 20 terminal configuration and functions copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 4-2. msp430fr588x, msp430fr588x1 signal descriptions terminal pm description rgc name no. general-purpose digital i/o p4.3/uca0somi/ 1 usci_a0: slave out, master in (spi mode), receive data (uart mode) uca0rxd/ucb1ste usci_b1: slave transmit enable (spi mode) general-purpose digital i/o usci_b0: clock signal input (spi slave mode), clock signal output (spi master mode) p1.4/ucb0clk/ uca0ste/ta1.0 2 usci_a0: slave transmit enable (spi mode) timer_a ta1 ccr0 capture: cci0a input, compare: out0 output general-purpose digital i/o usci_b0: slave transmit enable (spi mode) p1.5/ucb0ste/ uca0clk/ta0.0 3 usci_a0: clock signal input (spi slave mode), clock signal output (spi master mode) timer_a ta0 ccr0 capture: cci0a input, compare: out0 output general-purpose digital i/o usci_b0: slave in, master out (spi mode), i 2 c data (i 2 c mode) p1.6/ucb0simo/ ucb0sda/ta0.1 4 bsl data (i 2 c bsl) timer_a ta0 ccr1 capture: cci1a input, compare: out1 output general-purpose digital i/o usci_b0: slave out, master in (spi mode), i 2 c clock (i 2 c mode) p1.7/ucb0somi/ ucb0scl/ta0.2 5 bsl clock (i 2 c bsl) timer_a ta0 ccr2 capture: cci2a input, compare: out2 output general-purpose digital i/o p2.4/tb0.3 6 timer_b tb0 ccr3 capture: cci3a input, compare: out3 output general-purpose digital i/o p2.5/tb0.4 7 timer_b tb0 ccr4 capture: cci4a input, compare: out4 output general-purpose digital i/o p2.6/tb0.5/ esic1out 8 timer_b tb0 ccr5 capture: cci5a input, compare: out5 output esi comparator 1 output general-purpose digital i/o p2.7/tb0.6/ esic2out 9 timer_b tb0 ccr6 capture: cci6a input, compare: out6 output esi comparator 2 output general-purpose digital i/o p5.0/ta1.1/mclk 10 timer_a ta1 ccr1 capture: cci1a input, compare: out1 output mclk output general-purpose digital i/o p5.1/ta1.2 11 timer_a ta1 ccr2 capture: cci2a input, compare: out2 output general-purpose digital i/o timer_a ta1 ccr0 capture: cci0b input, compare: out0 output p5.2/ta1.0/ta1clk/ aclk 12 timer_a ta1 clock signal ta0clk input aclk output (divided by 1, 2, 4, or 8) general-purpose digital i/o p5.3/ucb1ste 13 usci_b1: slave transmit enable (spi mode) copyright ? 2014 ? 2015, texas instruments incorporated terminal configuration and functions 21 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com table 4-2. msp430fr588x, msp430fr588x1 signal descriptions (continued) terminal pm description rgc name no. general-purpose digital i/o p3.0/ucb1clk 14 usci_b1: clock signal input (spi slave mode), clock signal output (spi master mode) general-purpose digital i/o p3.1/ucb1simo/ucb1sda 15 usci_b1: slave in, master out (spi mode) usci_b1: i 2 c data (i 2 c mode) general-purpose digital i/o p3.2/ucb1somi/ucb1scl 16 usci_b1: slave out, master in (spi mode) usci_b1: i 2 c clock (i 2 c mode) dvss1 17 digital ground supply dvcc1 18 digital power supply test mode pin - select digital i/o on jtag pins test/sbwtck 19 spy-bi-wire input clock reset input active low; nonmaskable interrupt input rst/nmi/sbwtdio 20 spy-bi-wire data input/output general-purpose digital i/o test data output port pj.0/tdo/tb0outh/ 21 switch all pwm outputs high impedance input - timer_b tb0 smclk/srscg1 smclk output low-power debug: cpu status register scg1 general-purpose digital i/o test data input or test clock input pj.1/tdi/tclk/mclk/srscg0 22 mclk output low-power debug: cpu status register scg0 general-purpose digital i/o test mode select pj.2/tms/aclk/sroscoff 23 aclk output (divided by 1, 2, 4, or 8) low-power debug: cpu status register oscoff general-purpose digital i/o test clock pj.3/tck/cout/srcpuoff 24 comparator output low-power debug: cpu status register cpuoff general-purpose digital i/o p3.3/ta1.1/tb0clk 25 timer_a ta1 ccr1 capture: cci1a input, compare: out1 output timer_b tb0 clock signal tb0clk input general-purpose digital i/o usci_a1: slave in, master out (spi mode) p3.4/uca1simo/uca1txd/tb0.0 26 usci_a1: transmit data (uart mode) timer_b tb0 ccr0 capture: cci0a input, compare: out0 output 22 terminal configuration and functions copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 4-2. msp430fr588x, msp430fr588x1 signal descriptions (continued) terminal pm description rgc name no. general-purpose digital i/o usci_a1: slave out, master in (spi mode) p3.5/uca1somi/uca1rxd/tb0.1 27 usci_a1: receive data (uart mode) timer_b tb0 ccr1 capture: cci1a input, compare: out1 output general-purpose digital i/o p3.6/uca1clk/tb0.2 28 usci_a1: clock signal input (spi slave mode), clock signal output (spi master mode) timer_b tb0 ccr2 capture: cci2a input, compare: out2 output general-purpose digital i/o p3.7/uca1ste/tb0.3 29 usci_a1: slave transmit enable (spi mode) timer_b tb0 ccr3 capture: cci3b input, compare: out3 output general-purpose digital i/o p2.3/uca0ste/tb0outh 30 usci_a0: slave transmit enable (spi mode) switch all pwm outputs high impedance input - timer_b tb0 general-purpose digital i/o usci_a0: clock signal input (spi slave mode), clock signal output (spi master mode) p2.2/uca0clk/tb0.4/rtcclk 31 timer_b tb0 ccr4 capture: cci4b input, compare: out4 output rtc clock output for calibration general-purpose digital i/o usci_a0: slave out, master in (spi mode) usci_a0: receive data (uart mode) p2.1/uca0somi/uca0rxd/tb0.5/ 32 dmae0 bsl receive (uart bsl) timer_b tb0 ccr5 capture: cci5b input, compare: out5 output dma external trigger input general-purpose digital i/o usci_a0: slave in, master out (spi mode) usci_a0: transmit data (uart mode) p2.0/uca0simo/uca0txd/tb0.6/ 33 tb0clk bsl transmit (uart bsl) timer_b tb0 ccr6 capture: cci6b input, compare: out6 output timer_b tb0 clock signal tb0clk input dvss2 34 digital ground supply dvcc2 35 digital power supply general-purpose digital i/o esi test signal 4 p1.3/ esitest4/ta1.2/a3/c3 36 timer_a ta1 ccr2 capture: cci2a input, compare: out2 output analog input a3 comparator input c3 copyright ? 2014 ? 2015, texas instruments incorporated terminal configuration and functions 23 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com table 4-2. msp430fr588x, msp430fr588x1 signal descriptions (continued) terminal pm description rgc name no. general-purpose digital i/o timer_a ta1 ccr1 capture: cci1a input, compare: out1 output timer_a ta0 clock signal ta0clk input p1.2/ta1.1/ta0clk/cout/a2/c2 37 comparator output analog input a2 comparator input c2 general-purpose digital i/o timer_a ta0 ccr2 capture: cci2a input, compare: out2 output timer_a ta1 clock signal ta1clk input comparator output p1.1/ta0.2/ta1clk/ 38 cout/a1/c1/vref+/ veref+ analog input a1 comparator input c1 output of positive reference voltage input for an external positive reference voltage to the adc general-purpose digital i/o timer_a ta0 ccr1 capture: cci1a input, compare: out1 output dma external trigger input rtc clock output for calibration p1.0/ta0.1/dmae0/ rtcclk/a0/c0/ 39 vref-/veref- analog input a0 comparator input c0 output of negative reference voltage input for an external negative reference voltage to the adc general-purpose digital i/o esi channel 0 sensor excitation output and signal input p9.0/ esich0/esitest0/ a8/c8 40 esi test signal 0 analog input a8; comparator input c8 general-purpose digital i/o esi channel 1 sensor excitation output and signal input p9.1/ esich1/esitest1/ a9/c9 41 esi test signal 1 analog input a9 comparator input c9 general-purpose digital i/o esi channel 2 sensor excitation output and signal input p9.2/ esich2/esitest2/ a10/c10 42 esi test signal 2 analog input a10 comparator input c10 24 terminal configuration and functions copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 4-2. msp430fr588x, msp430fr588x1 signal descriptions (continued) terminal pm description rgc name no. general-purpose digital i/o esi channel 3 sensor excitation output and signal input p9.3/ esich3/esitest3/ a11/c11 43 esi test signal 3 analog input a11 comparator input c11 general-purpose digital i/o esi channel 0 signal input to comparator p9.4/ esici0/a12/c12 44 analog input a12 comparator input c12 general-purpose digital i/o esi channel 1 signal input to comparator p9.5/ esici1/a13/c13 45 analog input a13 comparator input c13 general-purpose digital i/o esi channel 2 signal input to comparator p9.6/ esici2/a14/c14 46 analog input a14 comparator input c14 general-purpose digital i/o esi channel 3 signal input to comparator p9.7/ esici3/a15/c15 47 analog input a15 comparator input c15 esidvcc 48 esi power supply esidvss 49 esi ground supply esici 50 esi scan if input to comparator esicom 51 esi common termination for scan if sensors avcc1 52 analog power supply avss3 53 analog ground supply general-purpose digital i/o pj.7/hfxout 54 output terminal of crystal oscillator xt2 general-purpose digital i/o pj.6/hfxin 55 input terminal for crystal oscillator xt2 avss1 56 analog ground supply general-purpose digital i/o pj.4/lfxin 57 input terminal for crystal oscillator xt1 general-purpose digital i/o pj.5/lfxout 58 output terminal of crystal oscillator xt1 avss2 59 analog ground supply general-purpose digital i/o usci_b1: slave in, master out (spi mode) p4.0/ucb1simo/ucb1sda/ mclk 60 usci_b1: i 2 c data (i 2 c mode) mclk output copyright ? 2014 ? 2015, texas instruments incorporated terminal configuration and functions 25 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com table 4-2. msp430fr588x, msp430fr588x1 signal descriptions (continued) terminal pm description rgc name no. general-purpose digital i/o usci_b1: slave out, master in (spi mode) p4.1/ucb1somi/ucb1scl/ aclk 61 usci_b1: i 2 c clock (i 2 c mode) aclk output (divided by 1, 2, 4, or 8) dvss3 62 digital ground supply dvcc3 63 digital power supply general-purpose digital i/o usci_a0: slave in, master out (spi mode) p4.2/uca0simo/uca0txd/ 64 ucb1clk usci_a0: transmit data (uart mode) usci_b1: clock signal input (spi slave mode), clock signal output (spi master mode) 26 terminal configuration and functions copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 4.5 pin multiplexing pin multiplexing for these devices is controlled by both register settings and operating modes (for example, if the device is in test mode). for details of the settings for each pin and schematics of the multiplexed ports, see section 6.11.23 . 4.6 connection of unused pins the correct termination of all unused pins is listed in table 4-3 . table 4-3. connection of unused pins (1) pin potential comment avcc dv cc avss dv ss px.0 to px.7 open switched to port function, output direction (pxdir.n = 1) r33/lcdcap dv ss or dv cc if not used the pin can be tied to either supplies. esidvcc dv cc esidvss dv ss esicom open esici open 47-k ? pullup or internal pullup selected with 10-nf (2.2 nf (2) ) rst/nmi dv cc or v cc pulldown pj.0/tdo the jtag pins are shared with general-purpose i/o function (pj.x). if pj.1/tdi open not being used, these should be switched to port function, output pj.2/tms direction. when used as jtag pins, these pins should remain open. pj.3/tck test open this pin always has an internal pulldown enabled. (1) any unused pin with a secondary function that is shared with general-purpose i/o should follow the px.0 to px.7 unused pin connection guidelines. (2) the pulldown capacitor should not exceed 2.2 nf when using devices with spy-bi-wire interface in spy-bi-wire mode or in 4-wire jtag mode with ti tools like fet interfaces or gang programmers. copyright ? 2014 ? 2015, texas instruments incorporated terminal configuration and functions 27 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 5 specifications 5.1 absolute maximum ratings (1) over operating free-air temperature range (unless otherwise noted) min max unit voltage applied at dvcc and avcc pins to v ss ? 0.3 4.1 v voltage difference between dvcc and avcc pins (2) 0.3 v v cc + 0.3 v voltage applied to any pin (3) ? 0.3 v (4.1 max) diode current at any device pin 2 ma storage temperature, t stg (4) ? 40 125 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) voltage differences between dvcc and avcc exceeding the specified limits may cause malfunction of the device including erroneous writes to ram and fram. (3) all voltages referenced to v ss . (4) higher temperature may be applied during board soldering according to the current jedec j-std-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. 5.2 esd ratings value unit human-body model (hbm), per ansi/esda/jedec js-001 (1) 1000 v (esd) electrostatic discharge v charged-device model (cdm), per jedec specification jesd22-c101 (2) 250 (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. pins listed as 1000 v may actually have higher performance. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. pins listed as 250 v may actually have higher performance. 5.3 recommended operating conditions typical data are based on v cc = 3.0 v, t a = 25 c unless otherwise noted. min nom max unit v cc supply voltage range applied at all dvcc, avcc, and esidvcc pins (1) (2) (3) 1.8 (4) 3.6 v v ss supply voltage applied at all dvss, avss, and esidvss pins 0 v t a operating free-air temperature ? 40 85 c t j operating junction temperature ? 40 85 c c dvcc capacitor value at dvcc and esidvcc (5) 1 ? 20% f no fram wait states (nwaitsx = 0) 0 8 (7) processor frequency (maximum mclk f system mhz frequency) (6) with fram wait states (nwaitsx = 1) (8) 0 16 (9) f aclk maximum aclk frequency 50 khz f smclk maximum smclk frequency 16 (9) mhz (1) it is recommended to power the dvcc, avcc, and esidvcc pins from the same source. at a minimum, during power up, power down, and device operation, the voltage difference between dvcc, avcc, and esidvcc must not exceed the limits specified in absolute maximum ratings . exceeding the specified limits may cause malfunction of the device including erroneous writes to ram and fram. (2) see table 5-1 for additional important information. (3) modules may have a different supply voltage range specification. refer to the specification of the respective module in this data sheet. (4) the minimum supply voltage is defined by the supervisor svs levels. see table 5-2 for the exact values. (5) connect a low-esr capacitor with at least the value specified and a maximum tolerance of 20% as close as possible to the dvcc and esidvcc pins. (6) modules may have a different maximum input clock specification. refer to the specification of the respective module in this data sheet. (7) dco settings and hf crystals with a typical value less or equal the specified max value are permitted. (8) wait states only occur on actual fram accesses; that is, on fram cache misses. ram and peripheral accesses are always executed without wait states. (9) dco settings and hf crystals with a typical value less or equal the specified max value are permitted. if a clock sources with a larger typical value is used, the clock must be divided in the clock system. 28 specifications copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 5.4 active mode supply current into v cc excluding external current (havok) over recommended operating free-air temperature (unless otherwise noted) (1) (2) frequency (f mclk = f smclk ) 1 mhz 4 mhz 8 mhz 12 mhz 16 mhz execution parameter v cc 0 wait states 0 wait states 0 wait states 1 wait states 1 wait states unit memory (nwaitsx = 0) (nwaitsx = 0) (nwaitsx = 0) (nwaitsx = 1) (nwaitsx = 1) typ max typ max typ max typ max typ max i am, fram_uni fram 3.0 v 210 640 1220 1475 1845 a (unified memory) (3) fram i am, fram (0%) (4) (5) 0% cache hit 3.0 v 375 1290 2525 2100 2675 a ratio fram i am, fram (50%) (4) (5) 50% cache hit 3.0 v 240 745 1440 1575 1990 a ratio fram i am, fram (66%) (4) (5) 66% cache hit 3.0 v 200 560 1070 1300 1620 a ratio fram i am, fram (75%) (4) (5) 75% cache hit 3.0 v 170 255 480 890 1085 1155 1310 1420 1620 a ratio fram i am, fram (100% (4) (5) 100% cache hit 3.0 v 110 235 420 640 730 a ratio i am, ram (6) (5) ram 3.0 v 130 320 585 890 1070 a i am, ram only (7) (5) ram 3.0 v 100 180 290 555 860 1040 1300 a (1) all inputs are tied to 0 v or to v cc . outputs do not source or sink any current. (2) characterized with program executing typical data processing. f aclk = 32768 hz, f mclk = f smclk = f dco at specified frequency, except for 12 mhz. for 12 mhz, f dco = 24 mhz and f mclk = f smclk = f dco /2. at mclk frequencies above 8 mhz, the fram requires wait states. when wait states are required, the effective mclk frequency (f mclk,eff ) decreases. the effective mclk frequency also depends on the cache hit ratio. smclk is not affected by the number of wait states or the cache hit ratio. the following equation can be used to compute f mclk,eff : f mclk,eff = f mclk / [wait states (1 ? cache hit ratio) + 1] for example, with 1 wait state and 75% cache hit ratio f mckl,eff = f mclk / [1 (1 ? 0.75) + 1] = f mclk / 1.25. (3) represents typical program execution. program and data reside entirely in fram. all execution is from fram. (4) program resides in fram. data resides in sram. average current dissipation varies with cache hit-to-miss ratio as specified. cache hit ratio represents number cache accesses divided by the total number of fram accesses. for example, a 75% ratio implies three of every four accesses is from cache, and the remaining are fram accesses. (5) see figure 5-1 for typical curves. each characteristic equation shown in the graph is computed using the least squares method for best linear fit using the typical data shown in section 5.4 . (6) program and data reside entirely in ram. all execution is from ram. (7) program and data reside entirely in ram. all execution is from ram. fram is off. copyright ? 2014 ? 2015, texas instruments incorporated specifications 29 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 5.5 typical characteristics, active mode supply currents i(am, cache hit ratio): program resides in fram. data resides in sram. average current dissipation varies with cache hit-to-miss ratio as specified. cache hit ratio represents number cache accesses divided by the total number of fram accesses. for example, a 75% ratio implies three of every four accesses is from cache, and the remaining are fram accesses. i(am, ramonly): program and data reside entirely in ram. all execution is from ram. fram is off. figure 5-1. typical active mode supply currents, no wait states 5.6 low-power mode (lpm0, lpm1) supply currents into v cc excluding external current over recommended operating free-air temperature (unless otherwise noted) (1) (2) frequency (f smclk ) parameter v cc 1 mhz 4 mhz 8 mhz 12 mhz 16 mhz unit typ max typ max typ max typ max typ max 2.2 v 75 105 165 250 230 i lpm0 a 3.0 v 85 120 115 175 260 240 275 2.2 v 40 65 130 215 195 i lpm1 a 3.0 v 40 65 65 130 215 195 220 (1) all inputs are tied to 0 v or to v cc . outputs do not source or sink any current. (2) current for watchdog timer clocked by smclk included. f aclk = 32768 hz, f mclk = 0 mhz, f smclk = f dco at specified frequency, except for 12 mhz: here f dco = 24 mhz and f smclk = f dco /2. 30 specifications copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 0 500 1000 1500 2000 2500 3000 0 1 2 3 4 5 6 7 8 9 active mode current [a] mclk frequency [mhz] i(am,0%) i(am,50%) i(am,66%) i(am,75%) i(am,100%) i(am,ramonly) c001 i(am,75%)[ua] = 103*f[mhz] + 68
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 5.7 low-power mode lpm2, lpm3, lpm4 supply currents (into v cc ) excluding external current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) ? 40 c 25 c 60 c 85 c parameter v cc unit typ max typ max typ max typ max 2.2 v 0.6 1.2 3.1 8.8 low-power mode 2, 12-pf i lpm2,xt12 a crystal (2) (3) (4) 3.0 v 0.6 1.2 2.2 3.1 8.8 20.8 2.2 v 0.5 1.1 3.0 8.7 low-power mode 2, 3.7-pf i lpm2,xt3.7 a crystal (2) (5) (4) 3.0 v 0.5 1.1 3.0 8.7 2.2 v 0.3 0.9 2.8 8.5 low-power mode 2, vlo, i lpm2,vlo a includes svs (6) 3.0 v 0.3 0.9 2.0 2.8 8.5 20.5 2.2 v 0.5 0.7 1.2 2.5 low-power mode 3, 12-pf i lpm3,xt12 a crystal, excludes svs (2) (3) (7) 3.0 v 0.5 0.7 1.0 1.2 2.5 6.4 low-power mode 3, 3.7-pf 2.2 v 0.4 0.6 1.1 2.4 i lpm3,xt3.7 crystal, excludes svs (2) (5) (8) a 3.0 v 0.4 0.6 1.1 2.4 (refer also to figure 5-2 ) 2.2 v 0.3 0.4 0.9 2.2 low-power mode 3, i lpm3,vlo a vlo, excludes svs (9) 3.0 v 0.3 0.4 0.8 0.9 2.2 6.1 low-power mode 3, 2.2 v 0.3 0.4 0.8 2.1 i lpm3,vlo, vlo, excludes svs, ram a ramoff 3.0 v 0.3 0.4 0.7 0.8 2.1 5.2 powered-down completely (10) (1) all inputs are tied to 0 v or to v cc . outputs do not source or sink any current. (2) not applicable for devices with hf crystal oscillator only. (3) characterized with a micro crystal ms1v-t1k crystal with a load capacitance of 12.5 pf. the internal and external load capacitance are chosen to closely match the required 12.5 pf load. (4) low-power mode 2, crystal oscillator test conditions: current for watchdog timer clocked by aclk and rtc clocked by xt1 included. current for brownout and svs included. cpuoff = 1, scg0 = 0 scg1 = 1, oscoff = 0 (lpm2), f xt1 = 32768 hz, f aclk = f xt1 , f mclk = f smclk = 0 mhz (5) characterized with a seiko ssp-t7-fl (smd) crystal with a load capacitance of 3.7 pf. the internal and external load capacitance are chosen to closely match the required 3.7-pf load. (6) low-power mode 2, vlo test conditions: current for watchdog timer clocked by aclk included. rtc disabled (rtchold = 1). current for brownout and svs included. cpuoff = 1, scg0 = 0 scg1 = 1, oscoff = 0 (lpm2), f xt1 = 0 hz, f aclk = f vlo , f mclk = f smclk = 0 mhz (7) low-power mode 3, 12-pf crystal excluding svs test conditions: current for watchdog timer clocked by aclk and rtc clocked by xt1 included. current for brownout included. svs disabled (svshe = 0). cpuoff = 1, scg0 = 1 scg1 = 1, oscoff = 0 (lpm3), f xt1 = 32768 hz, f aclk = f xt1 , f mclk = f smclk = 0 mhz activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional idle current. refer to the idle currents specified for the respective peripheral groups. (8) low-power mode 3, 3.7-pf crystal excluding svs test conditions: current for watchdog timer clocked by aclk and rtc clocked by xt1 included. current for brownout included. svs disabled (svshe = 0). cpuoff = 1, scg0 = 1 scg1 = 1, oscoff = 0 (lpm3), f xt1 = 32768 hz, f aclk = f xt1 , f mclk = f smclk = 0 mhz activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional idle current. refer to the idle currents specified for the respective peripheral groups. (9) low-power mode 3, vlo excluding svs test conditions: current for watchdog timer clocked by aclk included. rtc disabled (rtchold = 1). current for brownout included. svs disabled (svshe = 0). cpuoff = 1, scg0 = 1 scg1 = 1, oscoff = 0 (lpm3), f xt1 = 0 hz, f aclk = f vlo , f mclk = f smclk = 0 mhz activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional idle current. refer to the idle currents specified for the respective peripheral groups. (10) low-power mode 3, vlo excluding svs test conditions: current for watchdog timer clocked by aclk included. rtc disabled (rtchold = 1). ram disabled (rcctl0 = 5a55h). current for brownout included. svs disabled (svshe = 0). cpuoff = 1, scg0 = 1 scg1 = 1, oscoff = 0 (lpm3), f xt1 = 0 hz, f aclk = f vlo , f mclk = f smclk = 0 mhz activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional idle current. refer to the idle currents specified for the respective peripheral groups. copyright ? 2014 ? 2015, texas instruments incorporated specifications 31 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com low-power mode lpm2, lpm3, lpm4 supply currents (into v cc ) excluding external current (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) ? 40 c 25 c 60 c 85 c parameter v cc unit typ max typ max typ max typ max 2.2 v 0.4 0.5 0.9 2.3 low-power mode 4, includes i lpm4,svs a svs (11) 3.0 v 0.4 0.5 0.8 0.9 2.3 6.2 2.2 v 0.2 0.3 0.7 2.0 low-power mode 4, excludes i lpm4 a svs (12) 3.0 v 0.2 0.3 0.6 0.7 2.0 6.0 low-power mode 4, excludes 2.2 v 0.2 0.3 0.7 1.9 i lpm4,ramoff svs, ram powered-down a 3.0 v 0.2 0.3 0.6 0.7 1.9 5.1 completely (13) additional idle current if one or more modules from group a i idle,groupa 3.0v 0.02 0.3 1.2 a (refer to table 6-2 ) are activated in lpm3 or lpm4 additional idle current if one or more modules from group b i idle,groupb 3.0v 0.02 0.3 1.2 a (refer to table 6-2 ) are activated in lpm3 or lpm4 additional idle current if one or more modules from group c i idle,groupc 3.0v 0.02 0.38 1.5 a (refer to table 6-2 ) are activated in lpm3 or lpm4 additional idle current if one or more modules from group d i idle,groupd 3.0v 0.015 0.25 1.0 a (refer to table 6-2 ) are activated in lpm3 or lpm4 (11) low-power mode 4 including svs test conditions: current for brownout and svs included (svshe = 1). cpuoff = 1, scg0 = 1 scg1 = 1, oscoff = 1 (lpm4), f xt1 = 0 hz, f aclk = 0 hz, f mclk = f smclk = 0 mhz activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional idle current. refer to the idle currents specified for the respective peripheral groups. (12) low-power mode 4 excluding svs test conditions: current for brownout included. svs disabled (svshe = 0). cpuoff = 1, scg0 = 1 scg1 = 1, oscoff = 1 (lpm4), f xt1 = 0 hz, f aclk = 0 hz, f mclk = f smclk = 0 mhz activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional idle current. refer to the idle currents specified for the respective peripheral groups. (13) low-power mode 4 excluding svs test conditions: current for brownout included. svs disabled (svshe = 0). ram disabled (rcctl0 = 5a55h). cpuoff = 1, scg0 = 1 scg1 = 1, oscoff = 1 (lpm4), f xt1 = 0 hz, f aclk = 0 hz, f mclk = f smclk = 0 mhz activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional idle current. refer to the idle currents specified for the respective peripheral groups. 32 specifications copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 5.8 low-power mode with lcd supply currents (into v cc ) excluding external current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) temperature (t a ) parameter v cc ? 40 c 25 c 60 c 85 c unit typ max typ max typ max typ max low-power mode 3 (lpm3) i lpm3,xt12 current,12-pf crystal, lcd 4- lcd, 3.0 v 0.7 0.9 1.5 3.1 a mux mode, external biasing, ext. bias excludes svs (1) (2) low-power mode 3 (lpm3) i lpm3,xt12 current, 12-pf crystal, lcd 4- lcd, mux mode, internal biasing, 3.0 v 2.0 2.2 2.9 2.8 4.4 9.3 a int. bias charge pump disabled, excludes svs (1) (3) low-power mode 3 (lpm3) 2.2 v 5.0 5.2 5.8 7.4 current,12-pf crystal, lcd 4- i lpm3,xt12 mux mode, internal biasing, a lcd,cp 3.0 v 4.5 4.7 5.3 6.9 charge pump enabled, 1/3 bias, excludes svs (1) (4) (1) current for watchdog timer clocked by aclk and rtc clocked by xt1 included. current for brownout included. svs disabled (svshe = 0). cpuoff = 1, scg0 = 1 scg1 = 1, oscoff = 0 (lpm3), f xt1 = 32768 hz, f aclk = f xt1 , f mclk = f smclk = 0 mhz activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional idle current - idle current of group containing lcd module already included. refer to the idle currents specified for the respective peripheral groups. (2) lcdmx = 11 (4-mux mode), lcdrext = 1, lcdextbias = 1 (external biasing), lcd2b = 0 (1/3 bias), lcdcpen = 0 (charge pump disabled), lcdssel = 0, lcdprex = 101, lcddivx = 00011 (f lcd = 32768 hz / 32 / 4 = 256 hz) current through external resistors not included (voltage levels are supplied by test equipment). even segments s0, s2,... = 0, odd segments s1, s3,... = 1. no lcd panel load. (3) lcdmx = 11 (4-mux mode), lcdrext = 0, lcdextbias = 0 (internal biasing), lcd2b = 0 (1/3 bias), lcdcpen = 0 (charge pump disabled), lcdssel = 0, lcdprex = 101, lcddivx = 00011 (f lcd = 32768 hz / 32 / 4 = 256 hz) even segments s0, s2,...=0, odd segments s1, s3,...=1. no lcd panel load. (4) lcdmx = 11 (4-mux mode), lcdrext = 0, lcdextbias = 0 (internal biasing), lcd2b = 0 (1/3 bias), lcdcpen = 1 (charge pump enabled), vlcdx = 1000 (v lcd = 3 v typ.), lcdssel = 0, lcdprex = 101, lcddivx = 00011 (f lcd = 32768 hz / 32 / 4 = 256 hz) even segments s0, s2,...=0, odd segments s1, s3,...=1. no lcd panel load. c lcdcap = 10 f copyright ? 2014 ? 2015, texas instruments incorporated specifications 33 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 5.9 low-power mode lpmx.5 supply currents (into v cc ) excluding external current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) ? 40 c 25 c 60 c 85 c parameter v cc unit typ max typ max typ max typ max 2.2 v 0.4 0.45 0.55 0.75 low-power mode 3.5, 12-pf i lpm3.5,xt12 a crystal including svs (2) (3) (4) 3.0 v 0.4 0.45 0.7 0.55 0.75 1.6 2.2 v 0.3 0.35 0.4 0.65 low-power mode 3.5, 3.7-pf i lpm3.5,xt3.7 a crystal excluding svs (2) (5) (6) 3.0 v 0.3 0.35 0.4 0.65 2.2 v 0.2 0.2 0.25 0.35 low-power mode 4.5, including i lpm4.5,svs a svs (7) 3.0 v 0.2 0.2 0.4 0.25 0.35 0.7 2.2 v 0.02 0.02 0.03 0.14 low-power mode 4.5, i lpm4.5 a excluding svs (8) 3.0 v 0.02 0.02 0.03 0.13 0.5 (1) all inputs are tied to 0 v or to v cc . outputs do not source or sink any current. (2) not applicable for devices with hf crystal oscillator only. (3) characterized with a micro crystal ms1v-t1k crystal with a load capacitance of 12.5 pf. the internal and external load capacitance are chosen to closely match the required 12.5 pf load. (4) low-power mode 3.5, 1-pf crystal including svs test conditions: current for rtc clocked by xt1 included. current for brownout and svs included (svshe = 1). core regulator disabled. pmmregoff = 1; cpuoff = 1, scg0 = 1 scg1 = 1, oscoff = 1 (lpmx.5), f xt1 = 32768 hz, f aclk = f xt1 , f mclk = f smclk = 0 mhz (5) characterized with a seiko ssp-t7-fl (smd) crystal with a load capacitance of 3.7 pf. the internal and external load capacitance are chosen to closely match the required 3.7-pf load. (6) low-power mode 3.5, 3.7-pf crystal excluding svs test conditions: current for rtc clocked by xt1 included.current for brownout included. svs disabled (svshe = 0). core regulator disabled. pmmregoff = 1; cpuoff = 1, scg0 = 1 scg1 = 1, oscoff = 1 (lpmx.5), f xt1 = 32768 hz, f aclk = f xt1 , f mclk = f smclk = 0 mhz (7) low-power mode 4.5 including svs test conditions: current for brownout and svs included (svshe = 1). core regulator disabled. pmmregoff = 1; cpuoff = 1, scg0 = 1 scg1 = 1, oscoff = 1 (lpmx.5), f xt1 = 0 hz, f aclk = 0 hz, f mclk = f smclk = 0 mhz (8) low-power mode 4.5 excluding svs test conditions: current for brownout included. svs disabled (svshe = 0). core regulator disabled. pmmregoff = 1; cpuoff = 1, scg0 = 1 scg1 = 1, oscoff = 1 (lpmx.5), f xt1 = 0 hz, f aclk = 0 hz, f mclk = f smclk = 0 mhz 34 specifications copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 5.10 typical characteristics, low-power mode supply currents figure 5-2. lpm3 supply current vs temperature (lpm3,xt3.7) figure 5-3. lpm4 supply current vs temperature (lpm4,svs) figure 5-4. lpm3.5 supply current vs temperature figure 5-5. lpm4.5 supply current vs temperature (lpm4.5) (lpm3.5,xt3.7) copyright ? 2014 ? 2015, texas instruments incorporated specifications 35 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 -50 -25 0 25 50 75 100 axis title axis title @ 3.0v, svs off @ 2.2v, svs off c003 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 -50 -25 0 25 50 75 100 axis title axis title @ 3.0v, svs off @ 2.2v, svs off @ 3.0v, svs on @ 2.2v, svs on c004 0 0.5 1 1.5 2 2.5 3 -50 -25 0 25 50 75 100 lpm3 supply current [ a] temperature [ ? c] @ 3.0v, svs off @ 2.2v, svs off @ 3.0v, svs on @ 2.2v, svs on c003 0 0.5 1 1.5 2 2.5 3 -50 -25 0 25 50 75 100 lpm4 supply current [ a] temperature [ ? c] @ 3.0v, svs off @ 2.2v, svs off @ 3.0v, svs on @ 2.2v, svs on c001
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 5.11 typical characteristics, current consumption per module (1) module test conditions reference clock min typ max unit timer_a module input clock 3 a/mhz timer_b module input clock 5 a/mhz eusci_a uart mode module input clock 5.5 a/mhz eusci_a spi mode module input clock 3.5 a/mhz eusci_b spi mode module input clock 3.5 a/mhz eusci_b i 2 c mode, 100 kbaud module input clock 3.5 a/mhz rtc_c 32 khz 100 na mpy only from start to end of operation mclk 25 a/mhz crc16 only from start to end of operation mclk 2.5 a/mhz crc32 only from start to end of operation mclk 2.5 a/mhz (1) lcd_c: refer to section 5.8 . for other module currents not listed here, refer to the module-specific parameter sections. 36 specifications copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 5.12 thermal packaging characteristics (1) parameter package value (1) unit ja junction-to-ambient thermal resistance, still air (2) 49.8 c/w jc(top) junction-to-case (top) thermal resistance (3) 9.7 c/w jb junction-to-board thermal resistance (4) 26.0 c/w qfp-100 (pz) jb junction-to-board thermal characterization parameter 0.2 c/w jt junction-to-top thermal characterization parameter 25.7 c/w jc(bottom) junction-to-case (bottom) thermal resistance (5) n/a c/w ja junction-to-ambient thermal resistance, still air (2) 49.5 c/w jc(top) junction-to-case (top) thermal resistance (3) 14.7 c/w jb junction-to-board thermal resistance (4) 24.1 c/w qfp-80 (pm) jb junction-to-board thermal characterization parameter 0.7 c/w jt junction-to-top thermal characterization parameter 23.8 c/w jc(bottom) junction-to-case (bottom) thermal resistance (5) n/a c/w ja junction-to-ambient thermal resistance, still air (2) 55.3 c/w jc(top) junction-to-case (top) thermal resistance (3) 16.8 c/w jb junction-to-board thermal resistance (4) 26.8 c/w qfp-64 (pn) jb junction-to-board thermal characterization parameter 0.8 c/w jt junction-to-top thermal characterization parameter 26.5 c/w jc(bottom) junction-to-case (bottom) thermal resistance (5) n/a c/w ja junction-to-ambient thermal resistance, still air (2) 29.2 c/w jc(top) junction-to-case (top) thermal resistance (3) 13.9 c/w jb junction-to-board thermal resistance (4) 8.1 c/w qfn-64 (rgc) jb junction-to-board thermal characterization parameter 0.2 c/w jt junction-to-top thermal characterization parameter 8.0 c/w jc(bottom) junction-to-case (bottom) thermal resistance (5) 1.0 c/w (1) n/a = not applicable (2) the junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a jedec-standard, high-k board, as specified in jesd51-7, in an environment described in jesd51-2a. (3) the junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. no specific jedec- standard test exists, but a close description can be found in the ansi semi standard g30-88. (4) the junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the pcb temperature, as described in jesd51-8. (5) the junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. no specific jedec standard test exists, but a close description can be found in the ansi semi standard g30-88. copyright ? 2014 ? 2015, texas instruments incorporated specifications 37 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 5.13 timing and switching characteristics 5.13.1 power supply sequencing it is recommended to power the avcc, dvcc, and esidvcc pins from the same source. at a minimum, during power up, power down, and device operation, the voltage difference between avcc, dvcc, and esidvcc must not exceed the limits specified in absolute maximum ratings . exceeding the specified limits may cause malfunction of the device including erroneous writes to ram and fram. at power up, the device does not start executing code before the supply voltage reached v svsh+ if the supply rises monotonically to this level. table 5-1. brownout and device reset power ramp requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min max unit | ddv cc /d t | < 3 v/s (3) 0.7 1.66 v vcc_bor ? brownout power-down level (1) (2) v | ddv cc /d t | > 300 v/s (3) 0 v vcc_bor+ brownout power-up level (2) | ddv cc /d t | < 3 v/s (4) 0.79 1.68 v (1) in case of a supply voltage brownout scenario, the device supply voltages need to ramp down to the specified brownout power-down level v vcc_bor- before the voltage is ramped up again to ensure a reliable device start-up and performance according to the data sheet including the correct operation of the on-chip svs module. (2) fast supply voltage changes can trigger a bor reset even within the recommended supply voltage range. to avoid unwanted bor resets, the supply voltage must change by less than 0.05 v per microsecond ( 0.05 v/ s). following the data sheet recommendation for capacitor c dvcc should limit the slopes accordingly. (3) the brownout levels are measured with a slowly changing supply. with faster slopes the min level required to reset the device properly can decrease to 0 v. use the graph in figure 5-6 to estimate the v vcc_bor- level based on the down slope of the supply voltage. after removing vcc the down slope can be estimated based on the current consumption and the capacitance on dvcc: dv/dt = i/c with dv/dt: slope, i: current, c: capacitance. (4) the brownout levels are measured with a slowly changing supply. figure 5-6. brownout power-down level vs supply voltage down slope table 5-2. svs over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min typ max unit i svsh,lpm svs h current consumption, low power modes 170 300 na v svsh- svs h power-down level 1.75 1.80 1.85 v v svsh+ svs h power-up level 1.77 1.88 1.99 v v svsh_hys svs h hysteresis 40 120 mv t pd,svsh, am svs h propagation delay, active mode dv vcc /dt = ? 10 mv/ s 10 s 38 specifications copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 0 0.5 1 1.5 2 1 10 100 1000 10000 100000 brownout power-down level (v) supply voltage power-down slope (v/s) v vcc_bor- for reliable device start-up process-temp. corner case 1 typical process-temp. corner case 2 min limit
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 5.13.2 reset timing table 5-3. reset input over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter v cc min max unit t (rst) external reset pulse duration on rst (1) 2.2 v, 3.0 v 2 s (1) not applicable if rst/nmi pin configured as nmi. 5.13.3 clock specifications table 5-4. low-frequency crystal oscillator, lfxt (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit f osc = 32768 hz, lfxtbypass = 0, lfxtdrive = {0}, 3.0 v 180 t a = 25 c, c l,eff = 3.7 pf, esr 44 k f osc = 32768 hz, lfxtbypass = 0, lfxtdrive = {1}, 3.0 v 185 t a = 25 c, c l,eff = 6 pf, esr 40 k i vcc.lfxt current consumption na f osc = 32768 hz, lfxtbypass = 0, lfxtdrive = {2}, 3.0 v 225 t a = 25 c, c l,eff = 9 pf, esr 40 k f osc = 32768 hz, lfxtbypass = 0, lfxtdrive = {3}, 3.0 v 330 t a = 25 c, c l,eff = 12.5 pf, esr 40 k f lfxt lfxt oscillator crystal frequency lfxtbypass = 0 32768 hz measured at aclk, dc lfxt lfxt oscillator duty cycle 30% 70% f lfxt = 32768 hz lfxt oscillator logic-level f lfxt,sw lfxtbypass = 1 (2) (3) 10.5 32.768 50 khz square-wave input frequency lfxt oscillator logic-level dc lfxt, sw lfxtbypass = 1 30% 70% square-wave input duty cycle lfxtbypass = 0, lfxtdrive = {1}, 210 f lfxt = 32768 hz, c l,eff = 6 pf oscillation allowance for oa lfxt k ? lf crystals (4) lfxtbypass = 0, lfxtdrive = {3}, 300 f lfxt = 32768 hz, c l,eff = 12.5 pf (1) to improve emi on the lfxt oscillator, the following guidelines should be observed. ? keep the trace between the device and the crystal as short as possible. ? design a good ground plane around the oscillator pins. ? prevent crosstalk from other clock or data lines into oscillator pins lfxin and lfxout. ? avoid running pcb traces underneath or adjacent to the lfxin and lfxout pins. ? use assembly materials and processes that avoid any parasitic load on the oscillator lfxin and lfxout pins. ? if conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins. (2) when lfxtbypass is set, lfxt circuits are automatically powered down. input signal is a digital square wave with parametrics defined in the schmitt-trigger inputs section of this datasheet. duty cycle requirements are defined by dc lfxt, sw . (3) maximum frequency of operation of the entire device cannot be exceeded. (4) oscillation allowance is based on a safety factor of 5 for recommended crystals. the oscillation allowance is a function of the lfxtdrive settings and the effective load. in general, comparable oscillator allowance can be achieved based on the following guidelines, but should be evaluated based on the actual crystal selected for the application: ? for lfxtdrive = {0}, c l,eff = 3.7 pf. ? for lfxtdrive = {1}, c l,eff = 6 pf ? for lfxtdrive = {2}, 6 pf c l,eff 9 pf ? for lfxtdrive = {3}, 9 pf c l,eff 12.5 pf copyright ? 2014 ? 2015, texas instruments incorporated specifications 39 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com low-frequency crystal oscillator, lfxt (1) (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit integrated load capacitance at c lfxin 2 pf lfxin terminal (5) (6) integrated load capacitance at c lfxout 2 pf lfxout terminal (5) (6) f osc = 32768 hz, lfxtbypass = 0, lfxtdrive = {0}, 3.0 v 800 t a = 25 c, c l,eff = 3.7 pf t start,lfxt start-up time (7) ms f osc = 32768 hz, lfxtbypass = 0, lfxtdrive = {3}, 3.0 v 1000 t a = 25 c, c l,eff = 12.5 pf f fault,lfxt oscillator fault frequency (8) (9) 0 3500 hz (5) this represents all the parasitic capacitance present at the lfxin and lfxout terminals, respectively, including parasitic bond and package capacitance. the effective load capacitance, c l,eff can be computed as c in x c out / (c in + c out ), where c in and c out are the total capacitance at the lfxin and lfxout terminals, respectively. (6) requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. recommended effective load capacitance values supported are 3.7 pf, 6 pf, 9 pf, and 12.5 pf. maximum shunt capacitance of 1.6 pf. the pcb adds additional capacitance, so it must also be considered in the overall capacitance. it is recommended to verify that the recommended effective load capacitance of the selected crystal is met. (7) includes start-up counter of 1024 clock cycles. (8) frequencies above the max specification do not set the fault flag. frequencies in between the min and max specification may set the flag. a static condition or stuck at fault condition will set the flag. (9) measured with logic-level input frequency but also applies to operation with crystals. 40 specifications copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 5-5. high-frequency crystal oscillator, hfxt (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit f osc = 4 mhz, hfxtbypass = 0, hfxtdrive = 0, hffreq = 75 1 (2) t a = 25 c, c l,eff = 18 pf, typical esr, c shunt f osc = 8 mhz, hfxtbypass = 0, hfxtdrive = 1, hffreq = 1, 120 hfxt oscillator crystal t a = 25 c, c l,eff = 18 pf, typical esr, c shunt i dvcc.hfxt current hf mode at 3.0 v a typical esr f osc = 16 mhz, hfxtbypass = 0, hfxtdrive = 2, hffreq = 2, 190 t a = 25 c, c l,eff = 18 pf, typical esr, c shunt f osc = 24 mhz, hfxtbypass = 0, hfxtdrive = 3, hffreq = 3, 250 t a = 25 c, c l,eff = 18 pf, typical esr, c shunt hfxtbypass = 0, hffreq = 1 (2) (3) 4 8 hfxt oscillator crystal f hfxt hfxtbypass = 0, hffreq = 2 (3) 8.01 16 mhz frequency, crystal mode hfxtbypass = 0, hffreq = 3 (3) 16.01 24 hfxt oscillator duty dc hfxt measured at smclk, f hfxt = 16 mhz 40% 50% 60% cycle hfxtbypass = 1, hffreq = 0 (4) (3) 0.9 4 hfxt oscillator logic- hfxtbypass = 1, hffreq = 1 (4) (3) 4.01 8 f hfxt,sw level square-wave input mhz hfxtbypass = 1, hffreq = 2 (4) (3) 8.01 16 frequency, bypass mode hfxtbypass = 1, hffreq = 3 (4) (3) 16.01 24 hfxt oscillator logic- dc hfxt, sw level square-wave input hfxtbypass = 1 40% 60% duty cycle f osc = 4 mhz, hfxtbypass = 0, hfxtdrive = 0, hffreq = 1, 3.0 v 1.6 t a = 25 c, c l,eff = 16 pf t start,hfxt start-up time (5) ms f osc = 24 mhz , hfxtbypass = 0, hfxtdrive = 3, hffreq = 3, 3.0 v 0.6 t a = 25 c, c l,eff = 16 pf integrated load c hfxin capacitance at hfxin 2 pf terminai (6) (7) integrated load c hfxout capacitance at hfxout 2 pf terminai (6) (7) (1) to improve emi on the hfxt oscillator the following guidelines should be observed. ? keep the traces between the device and the crystal as short as possible. ? design a good ground plane around the oscillator pins. ? prevent crosstalk from other clock or data lines into oscillator pins hfxin and hfxout. ? avoid running pcb traces underneath or adjacent to the hfxin and hfxout pins. ? use assembly materials and processes that avoid any parasitic load on the oscillator hfxin and hfxout pins. ? if conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins. (2) hffreq = {0} is not supported for hfxt crystal mode of operation. (3) maximum frequency of operation of the entire device cannot be exceeded. (4) when hfxtbypass is set, hfxt circuits are automatically powered down. input signal is a digital square wave with parametrics defined in the schmitt-trigger inputs section of this datasheet. duty cycle requirements are defined by dc hfxt, sw . (5) includes start-up counter of 1024 clock cycles. (6) this represents all the parasitic capacitance present at the hfxin and hfxout terminals, respectively, including parasitic bond and package capacitance. the effective load capacitance, c l,eff can be computed as c in x c out / (c in + c out ), where c in and c out is the total capacitance at the hfxin and hfxout terminals, respectively. (7) requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. recommended effective load capacitance values supported are 14 pf, 16 pf, and 18 pf. maximum shunt capacitance of 7 pf. the pcb adds additional capacitance, so it must also be considered in the overall capacitance. it is recommended to verify that the recommended effective load capacitance of the selected crystal is met. copyright ? 2014 ? 2015, texas instruments incorporated specifications 41 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com high-frequency crystal oscillator, hfxt (1) (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit oscillator fault f fault,hfxt 0 800 khz frequency (8) (9) (8) frequencies above the max specification do not set the fault flag. frequencies in between the min and max might set the flag. a static condition or stuck at fault condition will set the flag. (9) measured with logic-level input frequency but also applies to operation with crystals. table 5-6. dco over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit measured at smclk, divide by 1, dco frequency range 1 mhz, f dco1 dcorsel = 0, dcofsel = 0, 1 3.5% mhz trimmed dcorsel = 1, dcofsel = 0 dco frequency range 2.7 mhz, measured at smclk, divide by 1, f dco2.7 2.667 3.5% mhz trimmed dcorsel = 0, dcofsel = 1 dco frequency range 3.5 mhz, measured at smclk, divide by 1, f dco3.5 3.5 3.5% mhz trimmed dcorsel = 0, dcofsel = 2 dco frequency range 4 mhz, measured at smclk, divide by 1, f dco4 4 3.5% mhz trimmed dcorsel = 0, dcofsel = 3 measured at smclk, divide by 1, dco frequency range 5.3 mhz, f dco5.3 dcorsel = 0, dcofsel = 4, 5.333 3.5% mhz trimmed dcorsel = 1, dcofsel = 1 measured at smclk, divide by 1, dco frequency range 7 mhz, f dco7 dcorsel = 0, dcofsel = 5, 7 3.5% mhz trimmed dcorsel = 1, dcofsel = 2 measured at smclk, divide by 1, dco frequency range 8 mhz, f dco8 dcorsel = 0, dcofsel = 6, 8 3.5% mhz trimmed dcorsel = 1, dcofsel = 3 dco frequency range 16 mhz, measured at smclk, divide by 1, f dco16 16 3.5% (1) mhz trimmed dcorsel = 1, dcofsel = 4 dco frequency range 21 mhz, measured at smclk, divide by 2, f dco21 21 3.5% (1) mhz trimmed dcorsel = 1, dcofsel = 5 dco frequency range 24 mhz, measured at smclk, divide by 2, f dco24 24 3.5% (1) mhz trimmed dcorsel = 1, dcofsel = 6 measured at smclk, divide by 1, no external divide, all f dco,dc duty cycle dcorsel/dcofsel settings except 48% 50% 52% dcorsel = 1, dcofsel = 5 and dcorsel = 1, dcofsel = 6 based on f signal = 10 khz and dco used for 12 bit sar adc sampling t dco, dco jitter source. this achieves > 74 db snr due 2 3 ns jitter to jitter (that is, it is limited by adc performance) df dco /dt dco temperature drift (2) 3.0 v 0.01 %/ o c (1) after a wakeup from lpm1, lpm2, lpm3 or lpm4 the dco frequency f dco might exceed the specified frequency range for a few clock cycles by up to 5% before settling into the specified steady state frequency range. (2) calculated using the box method: (max( ? 40 o c to 85 o c) ? min( ? 40 o c to 85 o c)) / min( ? 40 o c to 85 o c) / (85 o c ? ( ? 40 o c)) 42 specifications copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 5-7. internal very-low-power low-frequency oscillator (vlo) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit i vlo current consumption 100 na f vlo vlo frequency measured at aclk 6 9.4 14 khz df vlo /d t vlo frequency temperature drift measured at aclk (1) 0.2 %/ c df vlo /dv cc vlo frequency supply voltage drift measured at aclk (2) 0.7 %/v f vlo,dc duty cycle measured at aclk 40% 50% 60% (1) calculated using the box method: (max( ? 40 o c to 85 c) ? min( ? 40 o c to 85 c)) / min( ? 40 o c to 85 c) / (85 c ? ( ? 40 c)) (2) calculated using the box method: (max(1.8 to 3.6 v) ? min(1.8 to 3.6 v)) / min(1.8 to 3.6 v) / (3.6 v ? 1.8 v) table 5-8. module oscillator (modosc) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min typ max unit i modosc current consumption enabled 25 a f modosc modosc frequency 4.0 4.8 5.4 mhz f modosc /dt modosc frequency temperature drift (1) 0.08 %/ modosc frequency supply voltage f modosc /dv cc 1.4 %/v drift (2) dc modosc duty cycle measured at smclk, divide by 1 40% 50% 60% (1) calculated using the box method: (max( ? 40 o c to 85 c) ? min( ? 40 o c to 85 c)) / min( ? 40 o c to 85 c) / (85 c ? ( ? 40 c)) (2) calculated using the box method: (max(1.8 v to 3.6 v) ? min(1.8 v to 3.6 v)) / min(1.8 v to 3.6 v) / (3.6 v ? 1.8 v) copyright ? 2014 ? 2015, texas instruments incorporated specifications 43 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 5.13.4 wake-up characteristics table 5-9. wake-up times from low-power modes and reset over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) test parameter v cc min typ max unit conditions (additional) wake-up time to activate the fram in am if previously disabled by the fram t wake-up fram 6 10 s controller or from an lpm if immediate activation is selected for wake up 400 ns + t wake-up lpm0 wake-up time from lpm0 to active mode (1) 2.2 v, 3.0 v 1.5/f dco t wake-up lpm1 wake-up time from lpm1 to active mode (1) 2.2 v, 3.0 v 6 s t wake-up lpm2 wake-up time from lpm2 to active mode (1) 2.2 v, 3.0 v 6 s t wake-up lpm3 wake-up time from lpm3 to active mode (1) 2.2 v, 3.0 v 7 10 s t wake-up lpm4 wake-up time from lpm4 to active mode (1) 2.2 v, 3.0 v 7 10 s t wake-up lpm3.5 wake-up time from lpm3.5 to active mode (2) 2.2 v, 3.0 v 250 375 s svshe = 1 2.2 v, 3.0 v 250 375 s t wake-up lpm4.5 wake-up time from lpm4.5 to active mode (2) svshe = 0 2.2 v, 3.0 v 1 1.5 ms wake-up time from a rst pin triggered reset to t wake-up-rst 2.2 v, 3.0 v 250 375 s active mode (2) t wake-up-bor wake-up time from power-up to active mode (2) 2.2 v, 3.0 v 1 1.5 ms (1) the wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first externally observable mclk clock edge. mclk is sourced by the dco and the mclk divider is set to divide-by-1 (divmx = 000b, f mclk = f dco ). this time includes the activation of the fram during wake up. (2) the wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first instruction of the user program is executed. table 5-10. typical wake-up charge (1) parameter test conditions min typ max unit charge used for activating the fram in am or during wake-up q wake-up fram 15.1 nas from lpm0 if previously disabled by the fram controller. charge used for wake-up from lpm0 to active mode (with q wake-up lpm0 4.4 nas fram active) charge used for wake-up from lpm1 to active mode (with q wake-up lpm1 15.1 nas fram active) charge used for wake-up from lpm2 to active mode (with q wake-up lpm2 15.3 nas fram active) charge used for wake-up from lpm3 to active mode (with q wake-up lpm3 16.5 nas fram active) charge used for wake-up from lpm4 to active mode (with q wake-up lpm4 16.5 nas fram active) q wake-up lpm3.5 charge used for wake-up from lpm3.5 to active mode (2) 76 nas svshe = 1 77 q wake-up lpm4.5 charge used for wake-up from lpm4.5 to active mode (2) nas svshe = 0 77.5 q wake-up-reset charge used for reset from rst or bor event to active mode (2) 75 nas (1) charge used during the wake-up time from a given low-power mode to active mode. this does not include the energy required in active mode (for example, for an interrupt service routine). (2) charge required until start of user code. this does not include the energy required to reconfigure the device. 44 specifications copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 5.13.4.1 typical characteristics, average lpm currents vs wake-up frequency note: the average wake-up current does not include the energy required in active mode; for example, for an interrupt service routine or to reconfigure the device. figure 5-7. average lpm currents vs wake-up frequency at 25 c note: the average wake-up current does not include the energy required in active mode; for example, for an interrupt service routine or to reconfigure the device. figure 5-8. average lpm currents vs wake-up frequency at 85 c copyright ? 2014 ? 2015, texas instruments incorporated specifications 45 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 0.10 1.00 10.00 100.00 1000.00 10000.00 0.001 0.01 0.1 1 10 100 1000 10000 100000 average wake-up current [ a] wake-up frequency [hz] lpm0 lpm1 lpm2,xt12 lpm3,xt12 lpm3.5,xt12 c001 0.10 1.00 10.00 100.00 1000.00 10000.00 0.001 0.01 0.1 1 10 100 1000 10000 100000 average wake-up current [ a] wake-up frequency [hz] lpm0 lpm1 lpm2,xt12 lpm3,xt12 lpm3.5,xt12 c001
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 5.13.5 peripherals 5.13.5.1 digital i/os table 5-11. digital inputs over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit 2.2 v 1.2 1.65 v it+ positive-going input threshold voltage v 3.0 v 1.65 2.25 2.2 v 0.55 1.00 v it ? negative-going input threshold voltage v 3.0 v 0.75 1.35 2.2 v 0.44 0.98 v hys input voltage hysteresis (v it+ ? v it ? ) v 3.0 v 0.60 1.30 for pullup: v in = v ss r pull pullup or pulldown resistor 20 35 50 k for pulldown: v in = v cc c i,dig input capacitance, digital only port pins v in = v ss or v cc 3 pf input capacitance, port pins with shared analog c i,ana v in = v ss or v cc 5 pf functions (1) 2.2 v, i lkg(px.y) high-impedance input leakage current refer to notes (2) and (3) ? 20 +20 na 3.0 v ports with interrupt capability external interrupt timing (external trigger pulse (see block diagram and 2.2 v, t (int) 20 ns duration to set interrupt flag) (4) terminal function 3.0 v descriptions). 2.2 v, t (rst) external reset pulse duration on rst (5) 2 s 3.0 v (1) if the port pins pj.4/lfxin and pj.5/lfxout are used as digital i/os, they are connected by a 4-pf capacitor and a 35-m ? resistor in series. at frequencies of approximately 1 khz and lower, the 4-pf capacitor can add to the pin capacitance of pj.4/lfxin and/or pj.5/lfxout. (2) the input leakage current is measured with v ss or v cc applied to the corresponding pins, unless otherwise noted. (3) the input leakage of the digital port pins is measured individually. the port pin is selected for input and the pullup or pulldown resistor is disabled. (4) an external signal sets the interrupt flag every time the minimum interrupt pulse duration t (int) is met. it may be set by trigger signals shorter than t (int) . (5) not applicable if rst/nmi pin configured as nmi. 46 specifications copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 5-12. digital outputs over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit v cc ? i (ohmax) = ? 1 ma (1) v cc 0.25 2.2 v v cc ? i (ohmax) = ? 3 ma (2) v cc 0.60 v oh high-level output voltage v v cc ? i (ohmax) = ? 2 ma (1) v cc 0.25 3.0 v v cc ? i (ohmax) = ? 6 ma (2) v cc 0.60 v ss + i (olmax) = 1 ma (1) v ss 0.25 2.2 v v ss + i (olmax) = 3 ma (2) v ss 0.60 v ol low-level output voltage v v ss + i (olmax) = 2 ma (1) v ss 0.25 3.0 v v ss + i (olmax) = 6 ma (2) v ss 0.60 2.2 v 16 f px.y port output frequency (with load) (3) c l = 20 pf, r l (4) (5) mhz 3.0 v 16 aclk, mclk, or smclk at 2.2 v 16 f port_clk clock output frequency (3) configured output port mhz 3.0 v 16 c l = 20 pf (5) 2.2 v 4 15 t rise,dig port output rise time, digital only port pins c l = 20 pf ns 3.0 v 3 15 2.2 v 4 15 t fall,dig port output fall time, digital only port pins c l = 20 pf ns 3.0 v 3 15 2.2 v 6 15 port output rise time, port pins with shared t rise,ana c l = 20 pf ns analog functions 3.0 v 4 15 2.2 v 6 15 port output fall time, port pins with shared t fall,ana c l = 20 pf ns analog functions 3.0 v 4 15 (1) the maximum total current, i (ohmax) and i (olmax) , for all outputs combined should not exceed 48 ma to hold the maximum voltage drop specified. (2) the maximum total current, i (ohmax) and i (olmax) , for all outputs combined should not exceed 100 ma to hold the maximum voltage drop specified. (3) the port can output frequencies at least up to the specified limit - it might support higher frequencies. (4) a resistive divider with 2 r1 and r1 = 1.6 k between v cc and v ss is used as load. the output is connected to the center tap of the divider. c l = 20 pf is connected from the output to v ss . (5) the output voltage reaches at least 10% and 90% v cc at the specified toggle frequency. copyright ? 2014 ? 2015, texas instruments incorporated specifications 47 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 5.13.5.1.1 typical characteristics, digital outputs at 3.0 v and 2.2 v v cc = 2.2 v v cc = 3.0 v figure 5-9. typical low-level output current vs low-level figure 5-10. typical low-level output current vs low-level output voltage output voltage v cc = 2.2 v v cc = 3.0 v figure 5-11. typical high-level output current vs high-level figure 5-12. typical high-level output current vs high-level output voltage output voltage 48 specifications copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 0 10 20 30 0 0.5 1 1.5 2 2.5 3 low-level output current [ma] low-level output voltage [v] @ 25c @ 85c c001 p1.1 -15 -10 -5 0 0 0.5 1 1.5 2 high-level output current [ma] high-level output voltage [v] @ 25c @ 85c c001 p1.1 -30 -20 -10 0 0 0.5 1 1.5 2 2.5 3 high-level output current [ma] high-level output voltage [v] @ 25c @ 85c c001 p1.1 0 5 10 15 0 0.5 1 1.5 2 low-level output current [ma] low-level output voltage [v] @ 25c @ 85c c001 p1.1
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 5-13. pin-oscillator frequency, ports px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit px.y, c l = 10 pf (1) 3.0 v 1200 khz fo px.y pin-oscillator frequency px.y, c l = 20 pf (1) 3.0 v 650 khz (1) c l is the external load capacitance connected from the output to v ss and includes all parasitic effects such as pcb traces. 5.13.5.1.2 typical characteristics, pin-oscillator frequency v cc = 2.2 v one output active at a time. v cc = 3.0 v one output active at a time. figure 5-13. typical oscillation frequency vs load capacitance figure 5-14. typical oscillation frequency vs load capacitance copyright ? 2014 ? 2015, texas instruments incorporated specifications 49 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 100 1000 10 100 pin oscillator frequency [khz] external load capacitance (incl. board etc.) [pf] fitted 25c 85c c002 100 1000 10 100 pin oscillator frequency [khz] external load capacitance (incl. board etc.) [pf] fitted 25c 85c c002
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 5.13.5.2 timer_a and timer_b table 5-14. timer_a over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit internal: smclk, aclk 2.2 v, f ta timer_a input clock frequency external: taclk 16 mhz 3.0 v duty cycle = 50% 10% all capture inputs, minimum pulse 2.2 v, t ta,cap timer_a capture timing 20 ns duration required for capture 3.0 v table 5-15. timer_b over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit internal: smclk, aclk 2.2 v, f tb timer_b input clock frequency external: tbclk 16 mhz 3.0 v duty cycle = 50% 10% all capture inputs, minimum pulse 2.2 v, t tb,cap timer_b capture timing 20 ns duration required for capture 3.0 v 50 specifications copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 5.13.5.3 eusci table 5-16. eusci (uart mode) recommended operating conditions parameter conditions v cc min typ max unit internal: smclk, aclk f eusci eusci input clock frequency external: uclk 16 mhz duty cycle = 50% 10% bitclk clock frequency f bitclk 4 mhz (equals baud rate in mbaud) table 5-17. eusci (uart mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit ucglitx = 0 5 30 ucglitx = 1 20 90 2.2 v, t t uart receive deglitch time (1) ns 3.0 v ucglitx = 2 35 160 ucglitx = 3 50 220 (1) pulses on the uart receive input (ucxrx) shorter than the uart receive deglitch time are suppressed. thus the selected deglitch time can limit the max. useable baud rate. to ensure that pulses are correctly recognized their width should exceed the maximum specification of the deglitch time. table 5-18. eusci (spi master mode) recommended operating conditions parameter conditions v cc min typ max unit internal: smclk, aclk f eusci eusci input clock frequency 16 mhz duty cycle = 50% 10% table 5-19. eusci (spi master mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) parameter test conditions v cc min typ max unit t ste,lead ste lead time, ste active to clock ucstem = 1, ucmodex = 01 or 10 1 ucxcl k ste lag time, last clock to ste t ste,lag ucstem = 1, ucmodex = 01 or 10 1 cycles inactive ste access time, ste active to 2.2 v, t ste,acc ucstem = 0, ucmodex = 01 or 10 60 ns simo data out 3.0 v ste disable time, ste inactive to 2.2 v, t ste,dis ucstem = 0, ucmodex = 01 or 10 80 ns somi high impedance 3.0 v 2.2 v 40 t su,mi somi input data setup time ns 3.0 v 40 2.2 v 0 t hd,mi somi input data hold time ns 3.0 v 0 2.2 v 10 uclk edge to simo valid, t valid,mo simo output data valid time (2) ns c l = 20 pf 3.0 v 10 2.2 v 0 t hd,mo simo output data hold time (3) c l = 20 pf ns 3.0 v 0 (1) f ucxclk = 1/2t lo/hi with tl o/hi = max(t valid,mo(eusci) + t su,si(slave) , t su,mi(eusci) + t valid,so(slave) ). for the slave parameters t su,si(slave) and t valid,so(slave) , refer to the spi parameters of the attached slave. (2) specifies the time to drive the next valid data to the simo output after the output changing uclk clock edge. refer to the timing diagrams in figure 5-15 and figure 5-16 . (3) specifies how long data on the simo output is valid after the output changing uclk clock edge. negative values indicate that the data on the simo output can become invalid before the output changing clock edge observed on uclk. refer to the timing diagrams in figure 5-15 and figure 5-16 . copyright ? 2014 ? 2015, texas instruments incorporated specifications 51 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com figure 5-15. spi master mode, ckph = 0 figure 5-16. spi master mode, ckph = 1 52 specifications copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 t su,mi t hd,mi uclksomi simo t valid,mo ckpl = 0 ckpl = 1 t low/high t low/high 1/f ucxclk t ste,lead t ste,lag t ste,acc ucmodex = 01ucmodex = 10 ste t hd,mo t ste,dis t su,mi t hd,mi uclksomi simo t valid,mo ckpl = 0 ckpl = 1 t low/high t low/high 1/f ucxclk ste t ste,lead t ste,lag ucmodex = 01ucmodex = 10 t hd,mo t ste,acc t ste,dis
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 5-20. eusci (spi slave mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) parameter test conditions v cc min typ max unit 2.2 v 45 t ste,lead ste lead time, ste active to clock ns 3.0 v 40 2.2 v 2 t ste,lag ste lag time, last clock to ste inactive ns 3.0 v 3 2.2 v 45 t ste,acc ste access time, ste active to somi data out ns 3.0 v 40 2.2 v 50 ste disable time, ste inactive to somi high t ste,dis ns impedance 3.0 v 45 2.2 v 4 t su,si simo input data setup time ns 3.0 v 4 2.2 v 7 t hd,si simo input data hold time ns 3.0 v 7 2.2 v 35 uclk edge to somi valid, t valid,so somi output data valid time (2) ns c l = 20 pf 3.0 v 35 2.2 v 0 t hd,so somi output data hold time (3) c l = 20 pf ns 3.0 v 0 (1) f ucxclk = 1/2t lo/hi with tl o/hi max(t valid,mo(master) + t su,si(eusci) , t su,mi(master) + t valid,so(eusci) ). for the master parameters t su,mi(master) and t valid,mo(master) refer to the spi parameters of the attached slave. (2) specifies the time to drive the next valid data to the somi output after the output changing uclk clock edge. refer to the timing diagrams in figure 5-17 and figure 5-18 . (3) specifies how long data on the somi output is valid after the output changing uclk clock edge. refer to the timing diagrams in figure 5-17 and figure 5-18 . copyright ? 2014 ? 2015, texas instruments incorporated specifications 53 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com figure 5-17. spi slave mode, ckph = 0 figure 5-18. spi slave mode, ckph = 1 54 specifications copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 uclk ckpl = 0 ckpl = 1 somi simo t su,si t hd,si t valid,so t hd,so t low/high 1/f ucxclk t low/high t ste,dis t ste,acc ste t ste,lead t ste,lag ucmodex = 01ucmodex = 10 uclk ckpl = 0 ckpl = 1 somi simo t su,si t hd,si t valid,so t low/high 1/f ucxclk t low/high t ste,dis t ste,acc ste t ste,lead t ste,lag ucmodex = 01ucmodex = 10 t hd,so
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 5-21. eusci (i 2 c mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see figure 5-19 ) parameter test conditions v cc min typ max unit internal: smclk, aclk f eusci eusci input clock frequency external: uclk 16 mhz duty cycle = 50% 10% f scl scl clock frequency 2.2 v, 3.0 v 0 400 khz f scl = 100 khz 4.0 t hd,sta hold time (repeated) start 2.2 v, 3.0 v s f scl > 100 khz 0.6 f scl = 100 khz 4.7 t su,sta setup time for a repeated start 2.2 v, 3.0 v s f scl > 100 khz 0.6 t hd,dat data hold time 2.2 v, 3.0 v 0 ns t su,dat data setup time 2.2 v, 3.0 v 100 ns f scl = 100 khz 4.0 t su,sto setup time for stop 2.2 v, 3.0 v s f scl > 100 khz 0.6 f scl = 100 khz 4.7 bus free time between a stop and t buf s start condition f scl > 100 khz 1.3 ucglitx = 0 50 250 ucglitx = 1 25 125 pulse duration of spikes suppressed by t sp 2.2 v, 3.0 v ns input filter ucglitx = 2 12.5 62.5 ucglitx = 3 6.3 31.5 uccltox = 1 27 t timeout clock low time-out uccltox = 2 2.2 v, 3.0 v 30 ms uccltox = 3 33 figure 5-19. i 2 c mode timing copyright ? 2014 ? 2015, texas instruments incorporated specifications 55 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 sda scl t hd,dat t su,dat t hd,sta t high t low t buf t hd,sta t su,sta t sp t su,sto
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 5.13.5.4 lcd controller table 5-22. lcd_c - recommended operating conditions parameter conditions min nom max unit supply voltage range, lcdcpen = 1, 0000b < vlcdx 1111b v cc,lcd_c,cp en,3.6 charge pump enabled, 2.2 3.6 v (charge pump enabled, v lcd 3.6 v) v lcd 3.6 v supply voltage range, lcdcpen = 1, 0000b < vlcdx 1100b v cc,lcd_c,cp en,3.3 charge pump enabled, 2.0 3.6 v (charge pump enabled, v lcd 3.3 v) v lcd 3.3 v supply voltage range, v cc,lcd_c,int. bias internal biasing, charge lcdcpen = 0, vlcdext = 0 2.4 3.6 v pump disabled supply voltage range, v cc,lcd_c,ext. bias external biasing, charge lcdcpen = 0, vlcdext = 0 2.4 3.6 v pump disabled supply voltage range, external lcd voltage, v cc,lcd_c,vlcdext internal or external lcdcpen = 0, vlcdext = 1 2.0 3.6 v biasing, charge pump disabled external lcd voltage at lcdcap, internal or v lcdcap lcdcpen = 0, vlcdext = 1 2.4 3.6 v external biasing, charge pump disabled capacitor value on lcdcpen = 1, vlcdx > 0000b (charge c lcdcap lcdcap when charge 4.7 -20% 4.7 10 +20% f pump enabled) pump enabled aclk input frequency f aclk,in 30 32.768 40 khz range f frame = 1/(2 mux) f lcd with mux = 1 f lcd lcd frequency range 0 1024 hz (static) to 8 lcd frame frequency f frame,4mux (max) = 1/(2 4) f lcd (max) f frame,4mux 128 hz range = 1/(2 4) 1024 hz lcd frame frequency f frame,8mux (max) = 1/(2 4) f lcd (max) f frame,8mux 64 hz range = 1/(2 8) 1024 hz f lcd = 1024hz, all common lines equally c panel panel capacitance 10000 pf loaded analog input voltage at v r33 lcdcpen = 0, vlcdext = 1 2.4 v cc +0.2 v r33 v r03 + analog input voltage at lcdrext = 1, lcdextbias = 1, v r23,1/3bias v r13 2/3*(v r33 - v r33 v r23 lcd2b = 0 v r03 ) v r03 + analog input voltage at lcdrext = 1, lcdextbias = 1, v r13,1/3bias v r03 1/3*(v r33 - v r23 v r13 with 1/3 biasing lcd2b = 0 v r03 ) v r03 + analog input voltage at lcdrext = 1, lcdextbias = 1, v r13,1/2bias v r03 1/2*(v r33 - v r33 v r13 with 1/2 biasing lcd2b = 1 v r03 ) analog input voltage at v r03 r0ext = 1 v ss v r03 voltage difference v lcd -v r03 lcdcpen = 0, r0ext = 1 2.4 v cc +0.2 v between v lcd and r03 external lcd reference v lcdref voltage applied at vlcdrefx = 01 0.8 1.0 1.2 v lcdref 56 specifications copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 5-23. lcd_c electrical characteristics over operating free-air temperature range (unless otherwise noted) parameter test conditions v cc min typ max unit v lcd,0 vlcdx = 0000, vlcdext = 0 2.4 v to 3.6 v v cc v lcd,1 lcdcpen = 1, vlcdx = 0001b 2 v to 3.6 v 2.49 2.60 2.72 v lcd,2 lcdcpen = 1, vlcdx = 0010b 2 v to 3.6 v 2.66 v lcd,3 lcdcpen = 1, vlcdx = 0011b 2 v to 3.6 v 2.72 v lcd,4 lcdcpen = 1, vlcdx = 0100b 2 v to 3.6 v 2.78 v lcd,5 lcdcpen = 1, vlcdx = 0101b 2 v to 3.6 v 2.84 v lcd,6 lcdcpen = 1, vlcdx = 0110b 2 v to 3.6 v 2.90 v lcd,7 lcdcpen = 1, vlcdx = 0111b 2 v to 3.6 v 2.96 lcd voltage v v lcd,8 lcdcpen = 1, vlcdx = 1000b 2 v to 3.6 v 3.02 v lcd,9 lcdcpen = 1, vlcdx = 1001b 2 v to 3.6 v 3.08 v lcd,10 lcdcpen = 1, vlcdx = 1010b 2 v to 3.6 v 3.14 v lcd,11 lcdcpen = 1, vlcdx = 1011b 2 v to 3.6 v 3.20 v lcd,12 lcdcpen = 1, vlcdx = 1100b 2 v to 3.6 v 3.26 v lcd,13 lcdcpen = 1, vlcdx = 1101b 2.2 v to 3.6 v 3.32 v lcd,14 lcdcpen = 1, vlcdx = 1110b 2.2 v to 3.6 v 3.38 v lcd,15 lcdcpen = 1, vlcdx = 1111b 2.2 v to 3.6 v 3.32 3.44 3.6 lcdcpen = 1, vlcdx = 0111b, lcd voltage with external 2.96 v lcd,7,0.8 vlcdrefx = 01b, 2 v to 3.6 v v reference of 0.8 v 0.8 v v lcdref = 0.8 v lcdcpen = 1, vlcdx = 0111b, lcd voltage with external 2.96 v lcd,7,1.0 vlcdrefx = 01b, 2 v to 3.6 v v reference of 1.0 v 1.0 v v lcdref = 1.0 v lcdcpen = 1, vlcdx = 0111b, lcd voltage with external 2.96 v lcd,7,1.2 vlcdrefx = 01b, 2.2 v to 3.6 v v reference of 1.2 v 1.2 v v lcdref = 1.2 v voltage difference between v lcd = v lcd,x - v lcd,x-1 v lcd 40 60 80 mv consecutive vlcdx settings with x = 0010b to 1111b lcdcpen = 1, vlcdx = 1111b peak supply currents due to i cc,peak,cp external, with decoupling capacitor 2.2 v 600 a charge pump activities on dvcc supply 1 f time to charge c lcd when c lcd = 4.7 f, lcdcpen = 0 1, t lcd,cp,on 2.2 v 100 500 ms discharged vlcdx = 1111b maximum charge pump load i cp,load lcdcpen = 1, vlcdx = 1111b 2.2 v 50 a current lcd driver output impedance, r lcd,seg lcdcpen = 0, i load = 10 a 2.2 v 10 k ? segment lines lcd driver output impedance, r lcd,com lcdcpen = 0, i load = 10 a 2.2 v 10 k ? common lines copyright ? 2014 ? 2015, texas instruments incorporated specifications 57 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 5.13.5.5 adc table 5-24. 12-bit adc, power supply and input range conditions over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min nom max unit v(ax) analog input voltage range (1) all adc12 analog input pins ax 0 avcc v f adc12clk = modclk, adc12on = 1, 3.0 v 145 199 i(adc12_b) operating supply current into adc12pwrmd = 0, adc12dif = 0, single- a avcc plus dvcc terminals (2) (3) refon = 0, adc12shtx = 0, 2.2 v 140 190 ended mode adc12div = 0 f adc12clk = modclk, adc12on = 1, 3.0 v 175 245 i(adc12_b) operating supply current into adc12pwrmd = 0, adc12dif = 1, differential a avcc plus dvcc terminals (2) (3) refon = 0, adc12shtx= 0, 2.2 v 170 230 mode adc12div = 0 only one terminal ax can be selected c i input capacitance 2.2 v 10 15 pf at one time > 2 v 0.5 4 k r i input mux on resistance 0 v v(ax) avcc < 2 v 1 10 k (1) the analog input voltage range must be within the selected reference voltage range v r+ to v r- for valid conversion results. (2) the internal reference supply current is not included in current consumption parameter i(adc12_b). (3) approximately 60% (typical) of the total current into the avcc and dvcc terminal is from avcc. table 5-25. 12-bit adc, timing parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min typ max unit for specified performance of adc12 linearity frequency for specified parameters with adc12pwrmd = 0, f adc12clk 0.45 5.4 mhz performance if adc12pwrmd = 1, the maximum is 1/4 of the value shown here frequency for reduced f adc12clk linearity parameters have reduced performance 32.768 khz performance adc12div = 0, f adc12clk = f adc12osc from f adc12osc internal oscillator (1) 4 4.8 5.4 mhz modclk refon = 0, internal oscillator, f adc12clk = f adc12osc from modclk, 2.6 3.5 adc12winc = 0 t convert conversion time s external f adc12clk from aclk, mclk, or smclk, (2) adc12ssel 0 t adc12on turnon settling time of the adc see (3) 100 ns time adc must be off before note: t adc12off must be met to make sure that t adc12off 100 ns can be turned on again t adc12on time holds t sample sampling time r s = 400 , r i = 4 k , c i = 15 pf, c pext = 8 pf (4) 1 s (1) the adc12osc is sourced directly from modosc inside the ucs. (2) 14 x adc12div x 1/f adc12clk , if adc12winc=1 then 15 x adc12div x 1/f adc12clk (3) the condition is that the error in a conversion started after t adc12on is less than 0.5 lsb. the reference and input signal are already settled. (4) approximately 10 tau ( ) are needed to get an error of less than 0.5 lsb: t sample = ln(2 n+2 ) x (r s + r i ) x (c i + c pext ), where n = adc resolution =12, r s = external source resistance, c pext = external parasitic capacitance. 58 specifications copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 5-26. 12-bit adc, linearity parameters with external reference (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min typ max unit number of no missing code resolution 12 bits output-code bits integral linearity error (inl) e i 1.2 v v r+ - v r- av cc 1.8 lsb for differential input integral linearity error (inl) e i 1.2 v v r+ - v r- av cc 2.2 lsb for single ended inputs differential linearity error e d ? 0.99 +1.0 lsb (dnl) adc12vrsel = 0x2 or 0x4 without tlv calibration, e o offset error (2) (3) tlv calibration data can be used to improve the 0.5 1.5 mv parameter (4) with external voltage reference without internal buffer (adc12vrsel = 0x2 or 0x4) without tlv calibration, tlv calibration data can be used to improve the 0.8 2.5 parameter (4) , e g,ext gain error lsb vr+ = 2.5 v, vr- = avss with external voltage reference with internal buffer (adc12vrsel = 0x3), 1 20 vr+ = 2.5 v, vr- = avss with external voltage reference without internal buffer (adc12vrsel = 0x2 or 0x4) without tlv calibration, tlv calibration data can be used to improve the 1.4 3.5 parameter (4) , e t,ext total unadjusted error lsb vr+ = 2.5 v, vr- = avss with external voltage reference with internal buffer (adc12vrsel = 0x3), 1.4 21.0 vr+ = 2.5 v, vr- = avss (1) see table 5-28 and table 5-34 electrical sections for more information on internal reference performance and refer to the application report designing with the msp430fr59xx and msp430fr58xx adc ( slaa624 ) for details on optimizing adc performance for your application with the choice of internal versus external reference. (2) offset is measured as the input voltage (at which adc output transitions from 0 to 1) minus 0.5 lsb. (3) offset increases as ir drop increases when vr- is avss. (4) for details, see the device descriptor table section in the msp430fr58xx, msp430fr59xx, msp430fr68xx, and msp430fr69xx family user ' s guide ( slau367 ). table 5-27. 12-bit adc, dynamic performance for differential inputs with external reference (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min typ max unit snr signal-to-noise vr+ = 2.5 v, vr- = avss 68 71 db enob effective number of bits (2) vr+ = 2.5 v, vr- = avss 10.7 11.2 bits (1) see table 5-28 and table 5-34 electrical sections for more information on internal reference performance and refer to the application report designing with the msp430fr59xx and msp430fr58xx adc ( slaa624 ) for details on optimizing adc performance for your application with the choice of internal versus external reference. (2) enob = (sinad ? 1.76) / 6.02 table 5-28. 12-bit adc, dynamic performance for differential inputs with internal reference (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min typ max unit enob effective number of bits (2) vr+ = 2.5 v, vr- = avss 10.3 10.7 bits (1) see table 5-34 electrical section for more information on internal reference performance and refer to the application report designing with the msp430fr59xx and msp430fr58xx adc ( slaa624 ) for details on optimizing adc performance for your application with the choice of internal versus external reference. (2) enob = (sinad ? 1.76) / 6.02 copyright ? 2014 ? 2015, texas instruments incorporated specifications 59 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com table 5-29. 12-bit adc, dynamic performance for single-ended inputs with external reference (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min typ max unit snr signal-to-noise vr+ = 2.5 v, vr- = avss 64 68 db enob effective number of bits (2) vr+ = 2.5 v, vr- = avss 10.2 10.7 bits (1) see table 5-30 and table 5-34 electrical sections for more information on internal reference performance and refer to the application report designing with the msp430fr59xx and msp430fr58xx adc ( slaa624 ) for details on optimizing adc performance for your application with the choice of internal versus external reference. (2) enob = (sinad ? 1.76) / 6.02 table 5-30. 12-bit adc, dynamic performance for single-ended inputs with internal reference (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min typ max unit enob effective number of bits (2) vr+ = 2.5 v, vr- = avss 9.4 10.4 bits (1) see table 5-34 electrical section for more information on internal reference performance and refer to the application report designing with the msp430fr59xx and msp430fr58xx adc ( slaa624 ) for details on optimizing adc performance for your application with the choice of internal versus external reference. (2) enob = (sinad ? 1.76) / 6.02 table 5-31. 12-bit adc, dynamic performance with 32.768-khz clock over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min typ max unit reduced performance with f adc12clk from aclk lfxt enob effective number of bits (1) 32.768 khz, 10 bits vr+ = 2.5 v, vr- = avss (1) enob = (sinad ? 1.76) / 6.02 figure 5-20. typical temperature sensor voltage 60 specifications copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 500 550 600 650 700 750 800 850 900 950 -40 -20 0 20 40 60 80 typical temperature sensor voltage C mv ambient temperature C c
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 5-32. 12-bit adc, temperature sensor and built-in v 1/2 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min typ max unit adc12on = 1, adc12tcmap=1, v sensor see (1) (2) 700 mv t a = 0 c tc sensor see (2) adc12on = 1, adc12tcmap = 1 2.5 mv/ c sample time required if adctcmap = 1 and adc12on = 1, adc12tcmap = 1, t sensor(sample) 30 s channel max ? 1 is selected (3) error of conversion result 1 lsb avcc voltage divider for adc12batmap = 1 v 1/2 adc12on = 1, adc12batmap = 1 47.5% 50% 52.5% on max input channel i v 1/2 current for battery monitor during sample time adc12on = 1, adc12batmap = 1 38 63 a sample time required if adc12batmap = 1 t v 1/2 (sample) adc12on = 1, adc12batmap = 1 1.7 s and channel max is selected (4) (1) the temperature sensor offset can be as much as 30 c. a single-point calibration is recommended in order to minimize the offset error of the built-in temperature sensor. (2) the device descriptor structure contains calibration values for 30 c 3 c and 85 c 3 c for each of the available reference voltage levels. the sensor voltage can be computed as v sense = tc sensor * (temperature, c) + v sensor , where tc sensor and v sensor can be computed from the calibration values for higher accuracy. (3) the typical equivalent impedance of the sensor is 250 k . the sample time required includes the sensor-on time t sensor(on) . (4) the on-time t v1/2(on) is included in the sampling time t v1/2(sample) ; no additional on time is needed. table 5-33. 12-bit adc, external reference (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min typ max unit positive external reference voltage input veref+ v r+ v r+ > v r- 1.2 av cc v or veref- based on adc12vrsel bit negative external reference voltage input v r- v r+ > v r- 0 1.2 v veref+ or veref- based on adc12vrsel bit (v r+ - differential external reference voltage input v r+ > v r- 1.2 av cc v v r- ) 1.2 v v eref+ v avcc , v eref- = 0 v f adc12clk = 5 mhz, adc12shtx = 1h, 10 adc12dif = 0, adc12pwrmd = 0 i veref+ static input current singled ended input mode a i veref- 1.2 v v eref+ v avcc , v eref- = 0 v f adc12clk = 5 mhz, adc12shtx = 8h, 2.5 adc12dif = 0, adc12pwrmd = 01 1.2 v v eref+ v avcc , v eref- = 0 v f adc12clk = 5 mhz, adc12shtx = 1h, 20 adc12dif = 1, adc12pwrmd = 0 i veref+ static input current differential input mode a i veref- 1.2 v v eref+ v avcc , v eref- = 0 v f adc12clk = 5 mhz, adc12shtx = 8h, 5 adc12dif = 1, adc12pwrmd = 1 i veref+ peak input current with single-ended input 0 v v eref+ v avcc , adc12dif = 0 1.5 ma i veref+ peak input current with differential input 0 v v eref+ v avcc , adc12dif = 1 3 ma c veref+/- capacitance at veref+ or veref- terminal see (2) 10 f (1) the external reference is used during adc conversion to charge and discharge the capacitance array. the input capacitance, c i , is also the dynamic load for an external reference during conversion. the dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy. (2) two decoupling capacitors, 10 f and 470 nf, should be connected to veref to decouple the dynamic current required for an external reference source if it is used for the adc12_b. see also the msp430fr58xx, msp430fr59xx, msp430fr68xx, and msp430fr69xx family user ' s guide ( slau367 ). copyright ? 2014 ? 2015, texas instruments incorporated specifications 61 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 5.13.5.6 reference table 5-34. ref, built-in reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit refvsel = {2} for 2.5 v, refon = 1 2.7 v 2.5 1.5% positive built-in reference v ref+ refvsel = {1} for 2.0 v, refon = 1 2.2 v 2.0 1.5% v voltage output refvsel = {0} for 1.2 v, refon = 1 1.8 v 1.2 1.8% noise rms noise at vref (1) from 0.1 hz to 10 hz, refvsel = {0} 110 600 v vref adc buf_int buffer t a = 25 c , adc on, refvsel = {0}, v os_buf_int ? 12 +12 mv offset (2) refon = 1, refout = 0 vref adc buf_ext t a = 25 c, refvsel = {0} , refout = 1, v os_buf_ext ? 12 +12 mv buffer offset (3) refon = 1 or adc on refvsel = {0} for 1.2 v 1.8 avcc minimum voltage, av cc(min) positive built-in reference refvsel = {1} for 2.0 v 2.2 v active refvsel = {2} for 2.5 v 2.7 operating supply current i ref+ refon = 1 3 v 8 15 a into avcc terminal (4) adc on, refout = 0, refvsel = {0, 1, 2}, 3 v 225 355 adc12pwrmd = 0, adc on, refout = 1, refvsel = {0, 1, 2}, 3 v 1030 1660 adc12pwrmd = 0 operating supply current adc on, refout = 0, refvsel = {0, 1, 2}, i ref+_adc_buf 3 v 120 185 a into avcc terminal (4) adc12pwrmd = 1 adc on, refout = 1, refvsel = {0, 1, 2}, 3 v 545 895 adc12pwrmd = 1 adc off, refon=1, refout=1, 3 v 1085 1780 refvsel = {0, 1, 2} refvsel = {0, 1, 2}, avcc = avcc(min) for vref maximum load i o(vref+) each reference level, ? 1000 +10 a current, vref+ terminal refon = refout = 1 refvsel = {0, 1, 2}, vout/ io load-current regulation, i o(vref+) = +10 a or ? 1000 a, 2500 v/ma (vref+) vref+ terminal avcc = avcc(min) for each reference level, refon = refout = 1 capacitance at vref+ and c vref+/- refon = refout = 1 0 100 pf vref- terminals temperature coefficient of refvsel = {0, 1, 2}, refon = refout = 1, tc ref+ 18 50 ppm/k built-in reference t a = ? 40 c to 85 c (5) power supply rejection ratio av cc = av cc (min) - av cc(max) , t a = 25 c, psrr_dc 120 400 v/v (dc) refvsel = {0, 1, 2}, refon = refout = 1 power supply rejection ratio psrr_ac dav cc = 0.1 v at 1 khz 3.0 mv/v (ac) settling time of reference av cc = av cc (min) - av cc(max) , t settle 75 80 s voltage (6) refvsel = {0, 1, 2}, refon = 0 1 (1) internal reference noise affects adc performance when adc uses internal reference. refer to the application report designing with the msp430fr59xx and msp430fr58xx adc ( slaa624 ) for details on optimizing adc performance for your application with the choice of internal versus external reference. (2) buffer offset affects adc gain error and thus total unadjusted error. (3) buffer offset affects adc gain error and thus total unadjusted error. (4) the internal reference current is supplied through terminal avcc. (5) calculated using the box method: (max( ? 40 c to 85 c) ? min( ? 40 c to 85 c)) / min( ? 40 c to 85 c)/(85 c ? ( ? 40 c)). (6) the condition is that the error in a conversion started after t refon is less than 0.5 lsb. 62 specifications copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 5.13.5.7 comparator table 5-35. comparator_e over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit cepwrmd = 00, ceon = 1, cersx = 00 11 20 (fast) cepwrmd = 01, ceon = 1, cersx = 00 comparator operating 9 17 (medium) supply current into avcc, 2.2 v, i avcc_comp a excludes reference 3.0 v cepwrmd = 10, ceon = 1, cersx = 00 0.5 resistor ladder (slow), t a = 30 c cepwrmd = 10, ceon = 1, cersx = 00 1.3 (slow), t a = 85 c cereflx = 01, cersx = 10, refon = 0, quiescent current of 12 15 ceon = 0, cerefacc = 0 resistor ladder into avcc, 2.2 v, i avcc_ref a including ref module 3.0 v cereflx = 01, cersx = 10, refon = 0, 5 7 current ceon = 0, cerefacc = 1 cersx = 11, cereflx = 01, cerefacc = 0 1.8 v 1.17 1.2 1.23 cersx = 11, cereflx = 10, cerefacc = 0 2.2 v 1.92 2.0 2.08 cersx = 11, cereflx = 11, cerefacc = 0 2.7 v 2.40 2.5 2.60 v ref reference voltage level v cersx = 11, cereflx = 01, cerefacc = 1 1.8 v 1.10 1.2 1.245 cersx = 11, cereflx = 10, cerefacc = 1 2.2 v 1.90 2.0 2.08 cersx = 11, cereflx = 11, cerefacc = 1 2.7 v 2.35 2.5 2.60 common mode input v ic 0 v cc -1 v range cepwrmd = 00 ? 32 32 v offset input offset voltage cepwrmd = 01 ? 32 32 mv cepwrmd = 10 ? 30 30 cepwrmd = 00 or cepwrmd = 01 9 c in input capacitance pf cepwrmd = 10 9 on - switch closed 1 3 k ? r sin series input resistance off - switch open 50 m ? cepwrmd = 00, cef = 0, overdrive 20 mv 260 330 ns propagation delay, t pd cepwrmd = 01, cef = 0, overdrive 20 mv 350 460 response time cepwrmd = 10, cef = 0, overdrive 20 mv 15 s cepwrmd = 00 or 01, cef = 1, 700 1000 ns overdrive 20 mv, cefdly = 00 cepwrmd = 00 or 01, cef = 1, 1.0 1.8 overdrive 20 mv, cefdly = 01 propagation delay with t pd,filter filter active cepwrmd = 00 or 01, cef = 1, 2.0 3.5 s overdrive 20 mv, cefdly = 10 cepwrmd = 00 or 01, cef = 1, 4.0 7.0 overdrive 20 mv, cefdly = 11 ceon = 0 1, vin+, vin- from pins, 0.9 1.5 overdrive 20 mv, cepwrmd = 00 ceon = 0 1, vin+, vin- from pins, t en_cmp comparator enable time 0.9 1.5 s overdrive 20 mv, cepwrmd = 01 ceon = 0 1, vin+, vin- from pins, 15 100 overdrive 20 mv, cepwrmd = 10 copyright ? 2014 ? 2015, texas instruments incorporated specifications 63 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com comparator_e (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit ceon = 0 1, cereflx = 10, cersx = 11, refon = 0, overdrive 20 mv, 1 2 cepwrmd = 00 ceon = 0 1, cereflx = 10, cersx = 11, refon = 0, overdrive 20 mv, 1 2 cepwrmd = 01 ceon = 0 1, cereflx = 10, cersx = 11, refon = 0, overdrive 20 mv, 10 50 comparator and reference cepwrmd = 10 t en_cmp_vref ladder and reference s ceon = 0 1, cereflx = 10, cersx = 10, voltage enable time refon = 0, ceref0 = ceref1 = 0x0f, 2 5 overdrive 20 mv, cepwrmd = 00 ceon = 0 1, cereflx = 10, cersx = 10, refon = 0, ceref0 = ceref1 = 0x0f, 2 5 overdrive 20 mv, cepwrmd = 01 ceon = 0 1, cereflx = 10, cersx = 10, refon = 0, ceref0 = ceref1 = 0x0f, 10 50 overdrive 20 mv, cepwrmd = 10 ceon = 0 1, cereflx = 10, cersx = 10, refon = 1, ceref0 = ceref1 = 0x0f, 1 2 overdrive 20 mv, cepwrmd = 00 ceon = 0 1, cereflx = 10, cersx = 10, comparator and reference t en_cmp_rl refon = 1, ceref0 = ceref1 = 0x0f, 1 2 s ladder enable time overdrive 20 mv, cepwrmd = 01 ceon = 0 1, cereflx = 10, cersx = 10, refon = 1, ceref0 = ceref1 = 0x0f, 10 50 overdrive 20 mv, cepwrmd = 10 vin vin vin reference voltage for a vin = reference into resistor ladder, v ce_ref (n+0.9) (n+1) (n+1.1) v given tap n = 0 to 31 /32 /32 /32 64 specifications copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 5.13.5.8 scan interface table 5-36. extended scan interface, port drive, port timing over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions v cc min typ max unit voltage drop due to on-resistance v ol(esichx) of excitation transistor (see i(esichx) = 2 ma, esiten = 1 3 v 0.3 v figure 5-21 ) voltage drop due to on-resistance v oh(esichx) of damping transistor (1) (see i (esichx) = -200 a, esiten = 1 3 v 0.1 v figure 5-21 ) v ol(esicom) i (esicom) = 3 ma, esish = 1 2.2 v, 3 v 0 0.1 v v (esichx) = 0 v to av cc , port i esichx(tri-state) function disabled, 3 v -50 50 na esish = 1 (1) esicom = 1.5 v, supplied externally (see figure 5-22 ) figure 5-21. p6.x/esichx timing, esichx function selected figure 5-22. voltage drop due to on-resistance copyright ? 2014 ? 2015, texas instruments incorporated specifications 65 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 esichx) esichx) esichx) i ( esich.x esicom v ol( v oh( damping transistor excitation transistor t ex(esichx) esiex(tsm) esich.x t esich(x)
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com table 5-37. extended scan interface, sample capacitor/ri timing (1) over operating free-air temperature range (unless otherwise noted) parameter test conditions v cc min typ max unit sample capacitance on selected c shc(esichx) esiex(tsm) = 1, esish = 1 2.2 v, 3 v 7 9 pf esichx pin serial input resistance at the ri (esichx) esiex(tsm) = 1, esish = 1 2.2 v, 3 v 1.5 k esichx pin esishtsm (3) = 1, measurement t hold maximum hold time (2) sequence uses at least two esichx 62 s inputs, v sample < 3 mv (1) the minimum sampling time (7.6 x tau for 1/2 lsb accuracy) with maximum c shc(esichx) and ri (esichx) and ri (source) is t sample(min) ~ 7.6 c shc(esichx) (ri (esichx) + ri (source) ) with ri (source) estimated at 3 k , t sample(min) = 319 ns. (2) the sampled voltage at the sample capacitance varies less than 3 mv ( v sample ) during the hold time t hold . if the voltage is sampled after t hold , the sampled voltage may be any other value. (3) the control bit esivss was renamed to esishtsm to avoid confusion with supply pin naming. 66 specifications copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 5-38. extended scan interface, v cc /2 generator over operating free-air temperature range (unless otherwise noted) parameter test conditions v cc min typ max unit esi v cc /2 avcc = dvcc = esidvcc (connected v cc generator supply together), avss = dvss = esidvss 2.2 3.6 v voltage (connected together) c l at esicom pin = 470 nf 20%, f refresh(esicom) = 32768 hz, 370 500 t = 0 c to 85 c, esi v cc /2 r ext = 1k in series to c l i vmid generator 2.2 v, 3 v na quiescent current c l at esicom pin = 470 nf 20%, f refresh(esicom) = 32768 hz, 370 1600 t = -40 c to 85 c v cc /2 refresh f refresh(esicom) source clock = aclk 2.2 v, 3 v 32.768 khz frequency output voltage at c l at esicom pin = 470 nf 20%, av cc /2 - av cc /2 + v (esicom) av cc /2 v pin esicom i load = 1 a 0.07 0.07 time to reach 98% c l at esicom pin = 470 nf 20%, t on(esicom) after v cc /2 is 2.2 v, 3 v 1.7 6 ms f refresh(esicom) = 32768 hz switched on esien = 1, esivmiden (1) = 1, esish = 0, settling time to 2.2 v, 3 v 3 av cc = av cc - 100 mv, t vccsettle(esicom v cc /2560 (2 lsb) ms f refresh(esicom) = 32768 hz ) after av cc voltage change av cc = av cc + 100 mv, 2.2 v, 3 v 3 f refresh(esicom) = 32768 hz (1) the control bit esivcc2 was renamed to esivmiden to avoid confusion with supply pin naming. copyright ? 2014 ? 2015, texas instruments incorporated specifications 67 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com table 5-39. extended scan interface, 12-bit dac over operating free-air temperature range (unless otherwise noted) parameter test conditions v cc min typ max unit esidvcc = avcc = dvcc (connected together), v cc esi dac supply voltage 2.2 3.6 v esidvss = avss = dvss (connected together) 2.2 v 10 27 esi 12-bit dac operating supply i cc a current into avcc terminal (1) 3 v 14 35 resolution 12 bit r l = 1000 m , c l = 20 pf inl integral nonlinearity 2.2 v, 3 v -10 2 +10 lsb with autozeroing r l = 1000 m , c l = 20 pf, 2.2 v, 3 v -10 +10 lsb without autozeroing dnl differential nonlinearity r l = 1000 m , c l = 20 pf, 2.2 v, 3 v -10 +10 lsb with autozeroing e os offset error with autozeroing 2.2 v, 3 v 0 v e g gain error with autozeroing 2.2 v, 3 v 0.6% on time after av cc of esidac is t on(esidac) v +esica - v esidac = 6 mv 2.2 v, 3 v 2 s switched on esidac code = 0h a0h 2.2 v, 3 v 2 t settle(esidac) settling time s esidac code = a0h 0h 2.2 v, 3 v 2 (1) this parameter covers one esi 12-bit dac, either esi afe1 12-bit dac or esi afe2 12-bit dac. table 5-40. extended scan interface, comparator over operating free-air temperature range (unless otherwise noted) parameter test conditions v cc min typ max unit esidvcc = avcc = dvcc (connected together), v cc esi comparator supply voltage 2.2 3.6 v esidvss = avss = dvss (connected together) esi comparator operating supply i cc 2.2 v, 3 v 25 42 a current into avcc terminal (1) common mode input voltage v cc - v ic 2.2 v, 3 v 0 v range (2) 1 v v offset input offset voltage after autozeroing 2.2 v, 3 v -1.5 1.5 mv without autozeroing 40 temperature coefficient of v offset dv offset /dt 2.2 v, 3 v v/ c (3) after autozeroing 2 without autozeroing 0.3 v offset supply voltage (v cc ) dv offset /dv cc mv/v sensitivity (4) after autozeroing 0.2 v hys input voltage hysteresis v+ terminal = v- terminal = 0.5 v cc 2.2 v, 3 v 0.5 lsb on time after esica is switched v +esica - v esidac = +6 mv, t on(esica) 2.2 v, 3 v 2.0 s on v +esica = 0.5 x av cc v +esica - v esidac = -12 mv 6 mv, t settle(esica) settle time 2.2 v, 3 v 3.0 s v +esica = 0.5 x av cc v input = vcc / 2 t autozero autozeroing time of comparator 2.2 v, 3 v 3.0 s |v offset | < 1 mv (1) this parameter covers one single esi comparator; either esi afe1 comparator or esi afe2 comparator. (2) the comparator output is reliable when at least one of the input signals is within the common mode input voltage range. (3) calculated using the box method: (max( ? 40 c to 85 c) ? min( ? 40 c to 85 c)) / min( ? 40 c to 85 c) / (85 c ? ( ? 40 c)) (4) calculated using the box method: abs((voffset_vcc_max ? voffset_vcc_min)/(vcc_max ? vcc_min)) 68 specifications copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 5-41. extended scan interface, esiclk oscillator and tsm clock signals over operating free-air temperature range (unless otherwise noted) parameter test conditions v cc min typ max unit esidvcc = avcc = dvcc (connected together), v cc esi oscillator supply voltage 2.2 3.6 v esidvss = avss = dvss (connected together) f esiosc = 4.8 mhz, esidiv1x = 00b, 2.2 v 45 esi oscillator operating supply i cc esiclkgon = 1, esien = 1, no tsm a current 3 v 50 sequence running f esiosc_min esi oscillator at minimum setting t a = 30 o c, esiclkfq = 000000 2.3 mhz f esiosc_max esi oscillator at maximum setting t a = 30 o c, esiclkfq = 111111 7.9 mhz start-up time including t on(esiosc) f esiosc = 4.8mhz 2.2 v, 3 v 400 700 ns synchronization cycles esiosc frequency temperature f esiosc /dt f esiosc = 4.8 mhz 2.2 v, 3 v 0.15 %/ c drift (1) esiosc frequency supply f esiosc /dv cc f esiosc = 4.8 mhz 2.2 v, 3 v 2 %/v voltage drift (2) f esilfclk tsm low-frequency state clock 32.768 50 khz f esihfclk tsm high-frequency state clock 0.25 8 mhz (1) calculated using the box method: (max( ? 40 to 85 c) ? min( ? 40 to 85 c)) / min( ? 40 to 85 c) / (85 c ? ( ? 40 c)) (2) calculated using the box method: (max(2.2 v to 3.6 v) ? min(2.2 v to 3.6 v)) / min(2.2 v to 3.6 v) / (3.6 v ? 2.2 v) copyright ? 2014 ? 2015, texas instruments incorporated specifications 69 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 5.13.5.9 fram controller table 5-42. fram over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) test parameter min typ max unit conditions read and write endurance 10 15 cycles t j = 25 c 100 t retention data retention duration t j = 70 c 40 years t j = 85 c 10 i write current to write into fram i read (1) na i erase erase current n/a (2) na t write write time t read (3) ns read time, nwaitsx=0 1/f systems (4) ns t read read time, nwaitsx=1 2/f systems (4) ns (1) writing to fram does not require a setup sequence or additional power when compared to reading from fram. the fram read current i read is included in the active mode current consumption numbers i am,fram . (2) fram does not require a special erase sequence. (3) writing into fram is as fast as reading. (4) the maximum read (and write) speed is specified by f systems using the appropriate wait state settings (nwaitsx). 5.13.6 emulation and debug table 5-43. jtag and spy-bi-wire interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) test parameter min typ max unit conditions i jtag supply current adder when jtag active (but not clocked) 2.2 v, 3.0 v 40 100 a f sbw spy-bi-wire input frequency 2.2 v, 3.0 v 0 10 mhz t sbw,low spy-bi-wire low clock pulse duration 2.2 v, 3.0 v 0.04 15 s spy-bi-wire enable time (test high to acceptance of first clock t sbw, en 2.2 v, 3.0 v 110 s edge) (1) t sbw,rst spy-bi-wire return to normal operation time 15 100 s 2.2 v 0 16 mhz f tck tck input frequency - 4-wire jtag (2) 3.0 v 0 16 mhz r internal internal pulldown resistance on test 2.2 v, 3.0 v 20 35 50 k ? tclk/mclk frequency during jtag access, no fram access f tclk 16 mhz (limited by f system ) t tclk,low/high tclk low or high clock pulse duration, no fram access 25 ns tclk/mclk frequency during jtag access, including fram access f tclk,fram 4 mhz (limited by f system with no fram wait states) t tclk,fram,low/high tclk low or high clock pulse duration, including fram accesses 100 ns (1) tools accessing the spy-bi-wire interface need to wait for the t sbw,en time after pulling the test/sbwtck pin high before applying the first sbwtck clock edge. (2) f tck may be restricted to meet the timing requirements of the module selected. 70 specifications copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 6 detailed description 6.1 overview the texas instruments msp430fr688x and msp430fr588x families of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals. the architecture, combined with seven low-power modes is optimized to achieve extended battery life for example in flow metering applications. the devices features a powerful 16-bit risc cpu, 16-bit registers, and constant generators that contribute to maximum code efficiency. the msp430fr688x and msp430fr588x devices are microcontroller configurations with an extended scan interface (esi) for background water, heat and gas volume metering together with up to five 16-bit timers, comparator, universal serial communication interfaces (eusci) supporting uart, spi, and i 2 c, hardware multiplier, dma, real-time clock module with alarm capabilities, up to 83 i/o pins, and an high- performance 12-bit analog-to-digital converter (adc). the msp430fr698x devices also include an lcd module with contrast contral for displays with up to 320 segments. 6.2 cpu the msp430 cpu has a 16-bit risc architecture that is highly transparent to the application. all operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. the cpu is integrated with 16 registers that provide reduced instruction execution time. the register-to- register operation execution time is one cycle of the cpu clock. four of the registers, r0 to r3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. the remaining registers are general-purpose registers. peripherals are connected to the cpu using data, address, and control buses, and can be handled with all instructions. the instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. each instruction can operate on word and byte data. copyright ? 2014 ? 2015, texas instruments incorporated detailed description 71 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 6.3 operating modes the msp430 devices have one active mode and seven software selectable low-power modes of operation. an interrupt event can wake up the device from low-power modes lpm0 through lpm4, service the request, and restore back to the low-power mode on return from the interrupt program. low-power modes lpm3.5 and lpm4.5 disable the core supply to minimize power consumption. table 6-1. operating modes mode am lpm0 lpm1 lpm2 lpm3 lpm4 lpm3.5 lpm4.5 active shutdo shutdo , cpu off rtc wn wn active cpu off standby standby off fram (2) only with withou off (1) svs t svs maximum system 16 mhz 16 mhz 16 mhz 50 khz 50 khz 0 (3) 50 khz 0 (3) clock typical current 103 65 75 a at 40 a at consumption, 0.9 a 0.4 a 0.3 a 0.35 a 0.2 a 0.02 a a/mhz a/mhz 1mhz 1mhz t a = 25 c typical wakeup n/a instant. 6 s 6 s 7 s 7 s 250 s 250 s 1000 s time lf lf _ rtc _ wakeup events n/a all all i/o i/o i/o i/o i/o comp comp comp cpu on off off off off off reset reset standby (or fram on off (1) off off off off off off off (1) ) high-frequency available available available off off off reset reset peripherals low-frequency available available available available available off rtc reset peripherals (4) unclocked available available available available available available reset reset peripherals (5) (4) (4) mclk on off off off off off off off smclk opt. (6) opt. (6) opt. (6) off off off off off aclk on on on on on off off off full retention yes yes yes yes yes (7) yes (7) no no svs always always always opt. (8) opt. (8) opt. (8) opt. (8) on (9) off (10) brownout always always always always always always always always (1) fram disabled in fram controller (2) disabling the fram via the fram controller decreases the lpm current consumption, but the wake-up time can increase. if the wake- up is for fram access (for example, to fetch an interrupt vector), wake-up time is increased. if the wake-up is for a non-fram operation (for example, dma transfer to ram), wake-up time is not increased. (3) all clocks disabled (4) see section 6.3.1 , which describes the use of peripherals in lpm3 and lpm4. (5) " unclocked peripherals " are peripherals that do not require a clock source to operate; for example, the comparator and ref, or the eusci when operated as an spi slave. (6) controlled by smclkoff (7) using the ram controller, the ram can be completely powered down to save leakage; however, all data is lost. (8) activated svs (svshe = 1) results in higher current consumption. svs not included in typical current consumption. (9) svshe = 1 (10) svshe = 0 72 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 6.3.1 peripherals in lpm3 and lpm4 most peripherals can be activated to be operational in lpm3 if clocked by aclk. some modules are even operational in lpm4 because they do not require a clock to operate (for example, the comparator). activating a peripheral in lpm3 or lpm4 increases the current consumption due to its active supply current contribution but also due to an additional idle current. to limit the idle current adder certain peripherals are group together. to achieve optimal current consumption try to use modules within one group and to limit the number of groups with active modules. the grouping is shown in table 6-2 . modules not listed there are either already included in the standard lpm3 current consumption specifications or cannot be used in lpm3 or lpm4. the idle current adder is very small at room temperature (25 c) but increases at high temperatures (85 c). refer to the i idle current parameters in section 5.7 for details. table 6-2. peripheral groups group a group b group c group d timer ta0 timer ta1 timer ta2 timer ta3 extended scan interface comparator timer b0 lcd_c (esi) adc12_b eusci_a0 eusci_a1 ref_a eusci_b0 eusci_b1 copyright ? 2014 ? 2015, texas instruments incorporated detailed description 73 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 6.4 interrupt vector table and signatures the interrupt vectors, the power-up start address, and signatures are located in the address range 0ffffh to 0ff80h. table 6-3 summarizes the content of this address range. the power-up start address or reset vector is located at 0ffffh to 0fffeh. it contains the 16-bit address pointing to the start address of the application program. the interrupt vectors start at 0fffdh extending to lower addresses. each vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. the vectors programmed into the address range from 0ffffh to 0ffe0h are used as bsl password (if enabled by the corresponding signature) the signatures are located at 0ff80h extending to higher addresses. signatures are evaluated during device start-up. starting from address 0ff88h extending to higher addresses a jtag password can programmed. the password can extend into the interrupt vector locations using the interrupt vector addresses as additional bits for the password. refer to the chapter "system resets, interrupts, and operating modes, system control module (sys)" in the msp430fr58xx, msp430fr59xx, msp430fr68xx, msp430fr69xx family user's guide ( slau367 ) for details. table 6-3. interrupt sources, flags, vectors, and signatures system word interrupt source interrupt flag priority interrupt address system reset power-up, brownout, supply svshifg supervisor pmmrstifg external reset rst wdtifg watchdog time-out (watchdog wdtpw, frctlpw, mpupw, cspw, pmmpw mode) ubdifg wdt, frctl mpu, cs, pmm reset 0fffeh highest mpusegiifg, mpuseg1ifg, mpuseg2ifg, password violation mpuseg3ifg fram uncorrectable bit error accteifg detection pmmporifg, pmmborifg mpu segment violation (sysrstiv) (1) (2) fram access time error software por, bor system nmi vmaifg vacant memory access jmbnifg, jmboutifg jtag mailbox cbdifg, ubdifg (non)maskable 0fffch fram bit error detection mpusegiifg, mpuseg1ifg, mpuseg2ifg, mpu segment violation mpuseg3ifg (syssniv) (1) (3) user nmi nmiifg, ofifg external nmi (non)maskable 0fffah (sysuniv) (1) (3) oscillator fault comparator_e interrupt flags comparator_e maskable 0fff8h (ceiv) (1) timer_b tb0 tb0ccr0.ccifg maskable 0fff6h tb0ccr1.ccifg to tb0ccr6.ccifg, timer_b tb0 tb0ctl.tbifg maskable 0fff4h (tb0iv) (1) watchdog timer (interval timer wdtifg maskable 0fff2h mode) esiifg0...esiifg8 extended scan if maskable 0fff0h (esiiv) (1) (1) multiple source flags (2) a reset is generated if the cpu tries to fetch instructions from within peripheral space (3) (non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it. 74 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 6-3. interrupt sources, flags, vectors, and signatures (continued) system word interrupt source interrupt flag priority interrupt address uca0ifg: ucrxifg, uctxifg (spi mode) uca0ifg:ucsttifg, uctxcptifg, ucrxifg, eusci_a0 receive or transmit maskable 0ffeeh uctxifg (uart mode) (uca0iv) (1) ucb0ifg: ucrxifg, uctxifg (spi mode) ucb0ifg: ucalifg, ucnackifg, ucsttifg, ucstpifg, ucrxifg0, uctxifg0, ucrxifg1, eusci_b0 receive or transmit maskable 0ffech uctxifg1, ucrxifg2, uctxifg2, ucrxifg3, uctxifg3, uccntifg, ucbit9ifg (i 2 c mode) (ucb0iv) (1) adc12ifg0 to adc12ifg31 adc12loifg, adc12inifg, adc12hiifg, adc12_b maskable 0ffeah adc12rdyifg, adc12ovifg, adc12tovifg (adc12iv) (1) timer_a ta0 ta0ccr0.ccifg maskable 0ffe8h ta0ccr1.ccifg to ta0ccr2.ccifg, timer_a ta0 ta0ctl.taifg maskable 0ffe6h (ta0iv) (1) uca1ifg:ucrxifg, uctxifg (spi mode) uca1ifg:ucsttifg, uctxcptifg, ucrxifg, eusci_a1 receive or transmit maskable 0ffe4h uctxifg (uart mode) (uca1iv) (1) ucb1ifg: ucrxifg, uctxifg (spi mode) ucb1ifg: ucalifg, ucnackifg, ucsttifg, ucstpifg, ucrxifg0, uctxifg0, ucrxifg1, eusci_b1 receive or transmit) maskable 0ffe2h uctxifg1, ucrxifg2, uctxifg2, ucrxifg3, uctxifg3, uccntifg, ucbit9ifg (i 2 c mode) (ucb1iv) (1) dma0ctl.dmaifg, dma1ctl.dmaifg, dma dma2ctl.dmaifg maskable 0ffe0h (dmaiv) (1) timer_a ta1 ta1ccr0.ccifg maskable 0ffdeh ta1ccr1.ccifg to ta1ccr2.ccifg, timer_a ta1 ta1ctl.taifg maskable 0ffdch (ta1iv) (1) p1ifg.0 to p1ifg.7 i/o port p1 maskable 0ffdah (p1iv) (1) timer_a ta2 ta2ccr0.ccifg maskable 0ffd8h ta2ccr1.ccifg timer_a ta2 ta2ctl.taifg maskable 0ffd6h (ta2iv) (1) p2ifg.0 to p2ifg.7 i/o port p2 maskable 0ffd4h (p2iv) (1) timer_a ta3 ta3ccr0.ccifg maskable 0ffd2h ta3ccr1.ccifg timer_a ta3 ta3ctl.taifg maskable 0ffd0h (ta3iv) (1) p3ifg.0 to p3ifg.7 i/o port p3 maskable 0ffceh (p3iv) (1) p4ifg.0 to p4ifg.7 i/o port p4 maskable 0ffcch (p4iv) (1) lcd_c lcd_c interrupt flags (lcdciv) (1) maskable 0ffcah (reserved on msp430fr5xxx) rtcrdyifg, rtctevifg, rtcaifg, rtc_c rt0psifg, rt1psifg, rtcofifg maskable 0ffc8h lowest (rtciv) (1) reserved 0ffc6h copyright ? 2014 ? 2015, texas instruments incorporated detailed description 75 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com table 6-3. interrupt sources, flags, vectors, and signatures (continued) system word interrupt source interrupt flag priority interrupt address 0ffc4h reserved reserved (4) ? 0ff8ch ip encapsulation signature2 (4) 0ff8ah ip encapsulation signature1 (4) (6) 0ff88h bsl signature2 0ff86h signatures (5) bsl signature1 0ff84h jtag signature2 0ff82h jtag signature1 0ff80h (4) may contain a jtag password required to enable jtag access to the device. (5) signatures are evaluated during device start-up. see the " system resets, interrupts, and operating modes, system control module (sys) " chapter in the msp430fr58xx, msp430fr59xx, msp430fr68xx, msp430fr69xx family user ' s guide ( slau367 ) for details. (6) must not contain 0aaaah if used as jtag password and ip encapsulation functionality is not desired. 76 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 6.5 bootstrap loader (bsl) the bsl enables programming of the fram or ram using a uart serial interface (frxxxx devices) or an i 2 c interface (frxxxx1 devices). access to the device memory via the bsl is protected by an user- defined password. use of the bsl requires four pins as shown in table 6-4 . bsl entry requires a specific entry sequence on the rst/nmi/sbwtdio and test/sbwtck pins. for complete description of the features of the bsl and its implementation, see the msp430 memory programming user's guide ( slau265 ). table 6-4. bsl pin requirements and functions device signal bsl function rst/nmi/sbwtdio entry sequence signal test/sbwtck entry sequence signal p2.0 devices with uart bsl (frxxxx): data transmit p2.1 devices with uart bsl (frxxxx): data receive p1.6 devices with i 2 c bsl (frxxxx1): data p1.7 devices with i 2 c bsl (frxxxx1): clock vcc power supply vss ground supply 6.6 jtag operation 6.6.1 jtag standard interface the msp430 family supports the standard jtag interface which requires four signals for sending and receiving data. the jtag signals are shared with general-purpose i/o. the test/sbwtck pin is used to enable the jtag signals. in addition to these signals, the rst/nmi/sbwtdio is required to interface with msp430 development tools and device programmers. the jtag pin requirements are shown in table 6-5 . for further details on interfacing to development tools and device programmers, see the msp430 hardware tools user's guide ( slau278 ). table 6-5. jtag pin requirements and functions device signal direction function pj.3/tck in jtag clock input pj.2/tms in jtag state control pj.1/tdi/tclk in jtag data input, tclk input pj.0/tdo out jtag data output test/sbwtck in enable jtag pins rst/nmi/sbwtdio in external reset vcc power supply vss ground supply 6.6.2 spy-bi-wire interface in addition to the standard jtag interface, the msp430 family supports the 2-wire spy-bi-wire interface. spy-bi-wire can be used to interface with msp430 development tools and device programmers. the spy- bi-wire interface pin requirements are shown in table 6-6 . for further details on interfacing to development tools and device programmers, see the msp430 hardware tools user's guide ( slau278 ). copyright ? 2014 ? 2015, texas instruments incorporated detailed description 77 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com table 6-6. spy-bi-wire pin requirements and functions device signal direction function test/sbwtck in spy-bi-wire clock input rst/nmi/sbwtdio in, out spy-bi-wire data input/output vcc power supply vss ground supply 6.7 fram the fram can be programmed via the jtag port, spy-bi-wire (sbw), the bsl, or in-system by the cpu. features of the fram include: ? ultra-low-power ultra-fast write nonvolatile memory ? byte and word access capability ? programmable wait state generation ? error correction coding (ecc) note wait states for mclk frequencies > 8 mhz, wait states must be configured following the flow described in the "fram controller (frctrl)" chapter, section "wait state control" of the msp430fr58xx, msp430fr59xx, msp430fr68xx, msp430fr69xx family user's guide ( slau367 ). for important software design information regarding fram including but not limited to partitioning the memory layout according to application-specific code, constant, and data space requirements, the use of fram to optimize application energy consumption, and the use of the memory protection unit (mpu) to maximize application robustness by protecting the program code against unintended write accesses, see the application report msp430 ? fram technology ? how to and best practices ( slaa628 ). 6.8 ram the ram is made up of one sector. the sector can be completely powered down in lpm3 and lpm4 to save leakage; however, all data is lost during shutdown. 6.9 tiny ram the tiny ram can be used to hold data or a very small stack if the complete ram is powered down in lpm3 and lpm4. 6.10 memory protection unit including ip encapsulation the fram can be protected from inadvertent cpu execution, read or write access by the mpu. features of the mpu include: ? ip encapsulation with programmable boundaries (prevents reads from "outside" like jtag or non-ip software) in steps of 1kb. ? main memory partitioning programmable up to three segments in steps of 1kb. ? the access rights of each segment (main and information memory) can be individually selected. ? access violation flags with interrupt capability for easy servicing of access violations. 78 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 6.11 peripherals peripherals are connected to the cpu through data, address, and control buses and can be handled using all instructions. for complete module descriptions, see the msp430fr58xx, msp430fr59xx, msp430fr68xx, msp430fr69xx family user's guide ( slau367 ). 6.11.1 digital i/o up to eleven 8-bit i/o ports are implemented: ? all individual i/o bits are independently programmable. ? any combination of input, output, and interrupt conditions is possible. ? programmable pullup or pulldown on all ports. ? edge-selectable interrupt and lpm3.5 and lpm4.5 wakeup input capability is available for all pins of ports p1, p2, p3, and p4. ? read/write access to port-control registers is supported by all instructions. ? ports can be accessed byte-wise or word-wise in pairs. ? capacitive touch functionality is supported on all pins of ports p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, and pj. ? no cross-currents during start-up. note configuration of digital i/os after bor reset to prevent any cross-currents during start-up of the device all port pins are high- impedance with schmitt triggers and their module functions disabled. to enable the i/o functionality after a bor reset the ports must be configured first and then the locklpm5 bit must be cleared. for details refer to the "digital i/o" chapter, section "configuration after reset" in the msp430fr58xx, msp430fr59xx, msp430fr68xx, msp430fr69xx family user's guide ( slau367 ). 6.11.2 oscillator and clock system (cs) the clock system includes support for a 32-khz watch crystal oscillator xt1 (lf), an internal very-low- power low-frequency oscillator (vlo), an integrated internal digitally controlled oscillator (dco), and a high-frequency crystal oscillator xt2 (hf). the clock system module is designed to meet the requirements of both low system cost and low power consumption. a fail-safe mechanism exists for all crystal sources. the clock system module provides the following clock signals: ? auxiliary clock (aclk), sourced from a 32-khz watch crystal (lfxt1), the internal low-frequency oscillator (vlo), or a digital external low frequency ( < 50 khz) clock source. ? main clock (mclk), the system clock used by the cpu. mclk can be sourced from a high-frequency crystal (hfxt2), the internal digitally-controlled oscillator dco, a 32-khz watch crystal (lfxt1), the internal low-frequency oscillator (vlo), or a digital external clock source. ? sub-main clock (smclk), the subsystem clock used by the peripheral modules. smclk can be sourced by same sources made available to mclk. 6.11.3 power management module (pmm) the primary functions of the pmm are: ? supply regulated voltages to the core logic ? supervise voltages that are connected to the device (at dvcc pins) ? give reset signals to the device during power-on and power-off copyright ? 2014 ? 2015, texas instruments incorporated detailed description 79 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 6.11.4 hardware multiplier (mpy) the multiplication operation is supported by a dedicated peripheral module. the module performs operations with 32-bit, 24-bit, 16-bit, and 8-bit operands. the module supports signed and unsigned multiplication as well as signed and unsigned multiply-and-accumulate operations. 6.11.5 real-time clock (rtc_c) the rtc_c module contains an integrated real-time clock (rtc) with the following features implemented: ? calendar mode with leap year correction. ? general-purpose counter mode. the internal calendar compensates months with less than 31 days and includes leap year correction. the rtc_c also supports flexible alarm functions and offset-calibration hardware. rtc operation is available in lpm3.5 modes to minimize power consumption. 6.11.6 watchdog timer (wdt_a) the primary function of the wdt_a module is to perform a controlled system restart after a software problem occurs. if the selected time interval expires, a system reset is generated. if the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. note in watchdog mode the watchdog timer wdt prevents entry into lpm3.5 or lpm4.5 because this would deactivate the watchdog. table 6-7. wdt_a clocks normal operation wdtsselx (watchdog and interval timer mode) 00 smclk 01 aclk 10 vloclk 11 lfmodclk 6.11.7 system module (sys) the sys module handles many of the system functions within the device. these include power on reset and power up clear handling, nmi source selection and management, reset interrupt vector generators, boot strap loader entry mechanisms, as well as, configuration management (device descriptors). it also includes a data exchange mechanism via jtag called a jtag mailbox that can be used in the application. table 6-8. system module interrupt vector registers interrupt vector register address interrupt event value priority sysrstiv, system reset 019eh no interrupt pending 00h brownout (bor) 02h highest rstifg rst/nmi (bor) 04h pmmswbor software bor (bor) 06h lpmx.5 wakeup (bor) 08h security violation (bor) 0ah reserved 0ch 80 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 6-8. system module interrupt vector registers (continued) interrupt vector register address interrupt event value priority svshifg svsh event (bor) 0eh reserved 10h reserved 12h pmmswpor software por (por) 14h wdtifg watchdog time-out (puc) 16h wdtpw password violation (puc) 18h frctlpw password violation (puc) 1ah uncorrectable fram bit error detection (puc) 1ch peripheral area fetch (puc) 1eh pmmpw pmm password violation (puc) 20h mpupw mpu password violation (puc) 22h cspw cs password violation (puc) 24h mpusegpifg encapsulated ip memory segment 26h violation (puc) mpusegiifg information memory segment violation 28h (puc) mpuseg1ifg segment 1 memory violation (puc) 2ah mpuseg2ifg segment 2 memory violation (puc) 2ch mpuseg3ifg sgement 3 memory violation (puc) 2eh accteifg access time error (puc) (1) 30h reserved 32h to 3eh lowest syssniv, system nmi 019ch no interrupt pending 00h reserved 02h highest uncorrectable fram bit error detection 04h reserved 06h mpusegpifg encapsulated ip memory segment 08h violation mpusegiifg information memory segment violation 0ah mpuseg1ifg segment 1 memory violation 0ch mpuseg2ifg segment 2 memory violation 0eh mpuseg3ifg segment 3 memory violation 10h vmaifg vacant memory access 12h jmbinifg jtag mailbox input 14h jmboutifg jtag mailbox output 16h correctable fram bit error detection 18h reserved 1ah to 1eh lowest sysuniv, user nmi 019ah no interrupt pending 00h nmifg nmi pin 02h highest ofifg oscillator fault 04h reserved 06h reserved 08h reserved 0ah to 1eh lowest (1) indicates incorrect wait state settings. copyright ? 2014 ? 2015, texas instruments incorporated detailed description 81 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 6.11.8 dma controller the dma controller allows movement of data from one memory address to another without cpu intervention. for example, the dma controller can be used to move data from the adc10_b conversion memory to ram. using the dma controller can increase the throughput of peripheral modules. the dma controller reduces system power consumption by allowing the cpu to remain in sleep mode, without having to awaken to move data to or from a peripheral. table 6-9. dma trigger assignments (1) trigger channel 0 channel 1 channel 2 0 dmareq dmareq dmareq 1 ta0ccr0 ccifg ta0ccr0 ccifg ta0ccr0 ccifg 2 ta0ccr2 ccifg ta0ccr2 ccifg ta0ccr2 ccifg 3 ta1ccr0 ccifg ta1ccr0 ccifg ta1ccr0 ccifg 4 ta1ccr2 ccifg ta1ccr2 ccifg ta1ccr2 ccifg 5 ta2 ccr0 ccifg ta2 ccr0 ccifg ta2 ccr0 ccifg 6 ta3 ccr0 ccifg ta3 ccr0 ccifg ta3 ccr0 ccifg 7 tb0ccr0 ccifg tb0ccr0 ccifg tb0ccr0 ccifg 8 tb0ccr2 ccifg tb0ccr2 ccifg tb0ccr2 ccifg 9 reserved reserved reserved 10 reserved reserved reserved 11 reserved reserved reserved 12 reserved reserved reserved 13 reserved reserved reserved 14 uca0rxifg uca0rxifg uca0rxifg 15 uca0txifg uca0txifg uca0txifg 16 uca1rxifg uca1rxifg uca1rxifg 17 uca1txifg uca1txifg uca1txifg ucb0rxifg (spi) ucb0rxifg (spi) ucb0rxifg (spi) 18 ucb0rxifg0 (i 2 c) ucb0rxifg0 (i 2 c) ucb0rxifg0 (i 2 c) ucb0txifg (spi) ucb0txifg (spi) ucb0txifg (spi) 19 ucb0txifg0 (i 2 c) ucb0txifg0 (i 2 c) ucb0txifg0 (i 2 c) 20 ucb0rxifg1 (i 2 c) ucb0rxifg1 (i 2 c) ucb0rxifg1 (i 2 c) 21 ucb0txifg1 (i 2 c) ucb0txifg1 (i 2 c) ucb0txifg1 (i 2 c) 22 ucb0rxifg2 (i 2 c) ucb0rxifg2 (i 2 c) ucb0rxifg2 (i 2 c) 23 ucb0txifg2 (i 2 c) ucb0txifg2 (i 2 c) ucb0txifg2 (i 2 c) ucb1rxifg (spi) ucb1rxifg (spi) ucb1rxifg (spi) 24 ucb1rxifg0 (i 2 c) ucb1rxifg0 (i 2 c) ucb1rxifg0 (i 2 c) ucb1txifg (spi) ucb1txifg (spi) ucb1txifg (spi) 25 ucb1txifg0 (i 2 c) ucb1txifg0 (i 2 c) ucb1txifg0 (i 2 c) adc12 end of 26 adc12 end of conversion adc12 end of conversion conversion 27 reserved reserved reserved 28 esi esi esi 29 mpy ready mpy ready mpy ready 30 dma2ifg dma0ifg dma1ifg 31 dmae0 dmae0 dmae0 (1) if a reserved trigger source is selected, no trigger is generated. 82 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 6.11.9 enhanced universal serial communication interface (eusci) the eusci modules are used for serial data communication. the eusci module supports synchronous communication protocols such as spi (3 or 4 pin) and i 2 c, and asynchronous communication protocols such as uart, enhanced uart with automatic baudrate detection, and irda. the eusci_an module provides support for spi (3 pin or 4 pin), uart, enhanced uart, and irda. the eusci_bn module provides support for spi (3 pin or 4 pin) and i 2 c. two eusci_a modules and one or two eusci_b module are implemented. 6.11.10 extended scan interface (esi) the esi peripheral automatically scans sensors and measures linear or rotational motion with the lowest possible power consumption. the esi incorporates a v cc /2 generator, a comparator, and a 12-bit dac and supports up to four sensors. 6.11.11 timer_a ta0, timer_a ta1 ta0 and ta1 are 16-bit timers/counters (timer_a type) with three capture/compare registers each. each timer can support multiple capture/compares, pwm outputs, and interval timing. ta0 and ta1 have extensive interrupt capabilities. interrupts can be generated from the counter on overflow conditions and from each of the capture/compare registers. table 6-10. timer_a ta0 signal connections module device input module input module device output input port pin output output port pin signal signal block signal signal p1.2 or p6.7 or ta0clk taclk p7.0 aclk (internal) aclk timer n/a n/a smclk (internal) smclk p1.2 or p6.7 or ta0clk inclk p7.0 p1.5 ta0.0 cci0a p1.5 p7.1 or p10.1 ta0.0 cci0b p7.1 ccr0 ta0 ta0.0 dv ss gnd p10.1 dv cc v cc p1.0 p1.0 or p1.6 or ta0.1 cci1a p7.2 or p7.6 p1.6 p7.2 cout (internal) cci1b ccr1 ta1 ta0.1 p7.6 dv ss gnd adc12 (internal) adc12shsx = {1} dv cc v cc p1.1 or p1.7 or ta0.2 cci2a p1.1 p7.3 or p7.5 aclk (internal) cci2b p1.7 ccr2 ta2 ta0.2 dv ss gnd p7.3 dv cc v cc p7.5 copyright ? 2014 ? 2015, texas instruments incorporated detailed description 83 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com table 6-11. timer_a ta1 signal connections module device input module input module device output input port pin output output port pin signal signal block signal signal p1.1 or p4.4 or ta1clk taclk p5.2 aclk (internal) aclk timer n/a n/a smclk (internal) smclk p1.1 or p4.4 or ta1clk inclk p5.2 p1.4 or p4.5 ta1.0 cci0a p1.4 p5.2 or p10.2 ta1.0 cci0b p4.5 ccr0 ta0 ta1.0 dv ss gnd p5.2 dv cc v cc p10.2 p1.2 p1.2 or p3.3 or ta1.1 cci1a p4.6 or p5.0 p4.6 p3.3 cout (internal) cci1b ccr1 ta1 ta1.1 p5.0 dv ss gnd adc12 (internal) adc12shsx = {4} dv cc v cc p1.3 or p4.7 or ta1.2 cci2a p1.3 p5.1 or p7.7 aclk (internal) cci2b p4.7 ccr2 ta2 ta1.2 dv ss gnd p5.1 dv cc v cc p7.7 6.11.12 timer_a ta2 ta2 is a 16-bit timer/counter (timer_a type) with two capture/compare registers each and with internal connections only. the timer can support multiple capture/compares, pwm outputs, and interval timing. ta2 has extensive interrupt capabilities. interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. table 6-12. timer_a ta2 signal connections module output device input signal module input name module block device output signal signal cout (internal) taclk aclk (internal) aclk timer n/a smclk (internal) smclk from capacitive touch io inclk 0 (internal) ta3 ccr0 output cci0a ta3 cci0a input (internal) aclk (internal) cci0b ccr0 ta0 dv ss gnd dv cc v cc from capacitive touch io adc12 (internal) cci1a 0 (internal) adc12shsx = {5} cout (internal) cci1b ccr1 ta1 dv ss gnd dv cc v cc 84 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 6.11.13 timer_a ta3 ta3 is a 16-bit timer/counter (timer_a type) with five capture/compare registers each and with internal connections only. the timer can support multiple capture/compares, pwm outputs, and interval timing. ta3 has extensive interrupt capabilities. interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. table 6-13. timer_a ta3 signal connections module output device input signal module input name module block device output signal signal cout (internal) taclk aclk (internal) aclk timer n/a smclk (internal) smclk from capacitive touch io inclk 1 (internal) ta2 ccr0 output cci0a ta2 cci0a input (internal) aclk (internal) cci0b ccr0 ta0 dv ss gnd dv cc v cc from capacitive touch io adc12 (internal) cci1a 1 (internal) adc12shsx = {6} cout (internal) cci1b ccr1 ta1 dv ss gnd dv cc v cc dv ss cci2a esio0 (internal) cci2b ccr2 ta2 dv ss gnd dv cc v cc dv ss cci3a esio1 (internal) cci3b ccr3 ta3 dv ss gnd dv cc v cc dv ss cci4a esio2 (internal) cci4b ccr4 ta4 dv ss gnd dv cc v cc copyright ? 2014 ? 2015, texas instruments incorporated detailed description 85 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 6.11.14 timer_b tb0 tb0 is a 16-bit timer/counter (timer_b type) with seven capture/compare registers each. it can support multiple capture/compares, pwm outputs, and interval timing. it has extensive interrupt capabilities. interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. table 6-14. timer_b tb0 signal connections module device input module input module device output input port pin output output port pin signal signal block signal signal p2.0 or p3.3 or tb0clk tbclk p5.7 aclk (internal) aclk timer n/a n/a smclk (internal) smclk p2.0 or p3.3 or tb0clk inclk p5.7 p3.4 tb0.0 cci0a p3.4 p6.4 tb0.0 cci0b p6.4 ccr0 tb0 tb0.0 adc12 (internal) dv ss gnd adc12shsx = {2} dv cc v cc p3.5 or p6.5 tb0.1 cci1a p3.5 cout (internal) cci1b p6.5 ccr1 tb1 tb0.1 adc12 (internal) dv ss gnd adc12shsx = {3} dv cc v cc p3.6 or p6.6 tb0.2 cci2a p3.6 aclk (internal) cci2b p6.6 ccr2 tb2 tb0.2 dv ss gnd dv cc v cc p2.4 tb0.3 cci3a p2.4 p3.7 tb0.3 cci3b p3.7 ccr3 tb3 tb0.3 dv ss gnd dv cc v cc p2.5 tb0.4 cci4a p2.5 p2.2 tb0.4 cci4b p2.2 ccr4 tb4 tb0.4 dv ss gnd dv cc v cc p2.6 tb0.5 cci5a p2.6 p2.1 tb0.5 cci5b p2.1 ccr5 tb5 tb0.5 dv ss gnd dv cc v cc p2.7 tb0.6 cci6a p2.7 p2.0 tb0.6 cci6b p2.0 ccr6 tb6 tb0.6 dv ss gnd dv cc v cc 86 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 6.11.15 adc12_b the adc12_b module supports fast 12-bit analog-to-digital conversions with differential and single-ended inputs. the module implements a 12-bit sar core, sample select control, reference generator and a conversion result buffer. a window comparator with a lower and upper limit allows cpu independent result monitoring with three window comparator interrupt flags. the external trigger sources available are summarized in table 6-15 . the available multiplexing between internal and external analog inputs is listed in table 6-16 . table 6-15. adc12_b trigger signal connections adc12shsx connected trigger source binary decimal 000 0 software (adc12sc) 001 1 timer_a ta0 ccr1 output 010 2 timer_b tb0 ccr0 output 011 3 timer_b tb0 ccr1 output 100 4 timer_a ta1 ccr1 output 101 5 timer_a ta2 ccr1 output 110 6 timer_a ta3 ccr1 output 111 7 reserved (dvss) table 6-16. adc12_b external and internal signal mapping external internal control bit (control bit = 0) (control bit = 1) adc12batmap a31 battery monitor adc12tcmap a30 temperature sensor adc12ch0map a29 n/a (1) adc12ch1map a28 n/a (1) adc12ch2map a27 n/a (1) adc12ch3map a26 n/a (1) (1) n/a = no internal signal available on this device. 6.11.16 comparator_e the primary function of the comparator_e module is to support precision slope analog-to-digital conversions, battery voltage supervision, and monitoring of external analog signals. 6.11.17 crc16 the crc16 module produces a signature based on a sequence of entered data values and can be used for data checking purposes. the crc16 signature is based on the crc-ccitt standard. 6.11.18 crc32 the crc32 module produces a signature based on a sequence of entered data values and can be used for data checking purposes. the crc32 signature is based on the iso 3309 standard. 6.11.19 true random seed the device descriptor information (tlv) section contains a 128-bit true random seed that can be used to implement a deterministic random number generator. copyright ? 2014 ? 2015, texas instruments incorporated detailed description 87 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 6.11.20 shared reference (ref_a) the reference module (ref_a) is responsible for generation of all critical reference voltages that can be used by the various analog peripherals in the device. 6.11.21 lcd_c the lcd_c driver generates the segment and common signals required to drive a liquid crystal display (lcd). the lcd_c controller has dedicated data memories to hold segment drive information. common and segment signals are generated as defined by the mode. static, and 2-mux up to 8-mux lcds are supported. the module can provide a lcd voltage independent of the supply voltage with its integrated charge pump. it is possible to control the level of the lcd voltage and thus contrast by software. the module also provides an automatic blinking capability for individual segments in static, 2-mux, 3-mux, and 4-mux modes. 6.11.22 embedded emulation 6.11.22.1 embedded emulation module (eem) the eem supports real-time in-system debugging. the s version of the eem that is implemented on all devices has the following features: ? three hardware triggers or breakpoints on memory access ? one hardware trigger or breakpoint on cpu register write access ? up to four hardware triggers can be combined to form complex triggers or breakpoints ? one cycle counter ? clock control on module level 6.11.22.2 energytrace++ ? technology the devices implement circuitry to support energytrace++ technology. the energytrace++ technology allows you to observe information about the internal states of the microcontroller. these states include the cpu program counter (pc), the on or off status of the peripherals and the system clocks (regardless of the clock source), and the low-power mode currently in use. these states can always be read by a debug tool, even when the microcontroller sleeps in lpmx.5 modes. the activity of the following modules can be observed: ? mpy is calculating. ? wdt is counting. ? rtc is counting. ? adc: a sequence, sample, or conversion is active. ? ref: refbg or refgen active and bg in static mode. ? comp is on. ? eusci_a0 is transferring (receiving or transmitting) data. ? eusci_a1 is transferring (receiving or transmitting) data. ? eusci_b0 is transferring (receiving or transmitting) data. ? eusci_b1 is transferring (receiving or transmitting) data. ? tb0 is counting. ? ta0 is counting. ? ta1 is counting. ? ta2 is counting. ? ta3 is counting. ? lcd: timing generator is active. 88 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 ? esi: ? esi is active using lf clock source ? esi is active using hf clock source copyright ? 2014 ? 2015, texas instruments incorporated detailed description 89 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 6.11.23 input/output schematics 6.11.23.1 digital i/o functionality port p1, p2, p3, p4, p5, p6, p7, p8, p9, and p10 the port pins provide the following features: ? interrupt and wakeup from lpmx.5 capability for ports p1, p2, p3, and p4 ? capacitive touch functionality (see section 6.11.23.2 ) ? up to three digital module input or output functions ? lcd segment functionality (not all pins, package dependent) figure 6-1 shows the features and the corresponding control logic (not including the capacitive touch logic). it is applicable for all port pins p1.0 through p10.2 unless a dedicated schematic is available in the following sections. the module functions provided per pin and whether the direction is controlled by the module or by the port direction register for the selected secondary function are described in the pin function tables. a. the inputs from several pins toward a module are ored together. b. the direction is controlled either by the connected module or by the corresponding pxdir.y bit. refer to the pin function tables. note: functional representation only. figure 6-1. general port pin schematic 90 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 px.y/mod1/mod2/mod3/sz pxsel1.y pxdir.y pxin.y to module 1 (a) to module 2 (a) to module 3 (a) from module 1 pxout.y 1 0 dvssdvcc 1 pad logic direction0: input 1: output pxren.y 0 1 0 01 0 1 1 pxsel0.y 0 1 0 01 0 1 1 from module 2 from module 2 (b) from module 1 (b) from module 3 (b) from module 3 sz lcdsz
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 6.11.23.2 capacitive touch functionality port p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, and pj figure 6-2 shows the capacitive touch functionality that all port pins provide. the capacitive touch functionality is controlled using the capacitive touch io control registers captio0ctl and captio1ctl as described in the msp430fr58xx family user's guide ( slau367 ). the capacitive touch functionality is not shown in the other pin schematics. note: functional representation only. figure 6-2. capacitive touch io functionality copyright ? 2014 ? 2015, texas instruments incorporated detailed description 91 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 01 01 1 pxren.y pxout.y direction control analog enable capacitive touch enable 0 output signal dvss dvcc input signal px.y capacitive touch signal 0 capacitive touch signal 1 en d q capacitive touch enable 1
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 6.11.23.3 port p1, p1.0 to p1.3, input/output with schmitt trigger a. the inputs from several pins toward a module are ored together. note: functional representation only. 92 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 p1.0/ta0.1/dmae0/rtcclk/ a0/c0/vref-/veref- p1.1/ta0.2/ta1clk/cout/ a1/c1vref+/veref+ p1.2/ta1.1/ta0clk/cout/a2/c2 p1.3/ta1.2/esitest4/a3/c3 p1sel1.x p1dir.x p1in.x from module 1 p1out.x 1 0 dvssdvcc 1 to comparator from comparator pad logic to adc from adc bus keeper direction0: input 1: output cepd.x p1ren.x 0 1 0 01 0 1 1 p1sel0.x 0 1 0 01 0 1 1 from module 2 (adc) reference (p1.0, p1.1) dvss to module 1 (a) to module 2 (a)
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 6-17. port p1 (p1.0 to p1.3) pin functions control bits and signals (1) pin name (p1.x) x function p1dir.x p1sel1.x p1sel0.x p1.0/ta0.1/dmae0/rtcclk/a0/c0/ 0 p1.0 (i/o) i: 0; o: 1 0 0 vref-/veref- ta0.cci1a 0 0 1 ta0.1 1 dmae0 0 1 0 rtcclk (2) 1 a0, c0, vref-, veref- (3) (4) x 1 1 p1.1/ta0.2/ta1clk/cout/a1/c1/ 1 p1.1 (i/o) i: 0; o: 1 0 0 vref+/veref+ ta0.cci2a 0 0 1 ta0.2 1 ta1clk 0 1 0 cout (5) 1 a1, c1, vref+, veref+ (3) (4) x 1 1 p1.2/ta1.1/ta0clk/cout/a2/c2 2 p1.2 (i/o) i: 0; o: 1 0 0 ta1.cci1a 0 0 1 ta1.1 1 ta0clk 0 1 0 cout (6) 1 a2, c2 (3) (4) x 1 1 p1.3/ta1.2/ esitest4/a3/c3 3 p1.3 (i/o) i: 0; o: 1 0 0 ta1.cci2a 0 0 1 ta1.2 1 n/a 0 1 0 esitest4 1 a3, c3 (3) (4) x 1 1 (1) x = don ' t care (2) note: do not use this pin as rtcclk output if the dmae0 functionality is used on any other pin. select an alternative rtcclk output pin. (3) setting p1sel1.x and p1sel0.x disables the output driver and the input schmitt trigger to prevent parasitic cross currents when applying analog signals. (4) setting the cepd.x bit of the comparator disables the output driver and the input schmitt trigger to prevent parasitic cross currents when applying analog signals. selecting the cx input pin to the comparator multiplexer with the input select bits in the comparator module automatically disables output driver and input buffer for that pin, regardless of the state of the associated cepd.x bit. (5) note: do not use this pin as cout output if the ta1clk functionality is used on any other pin. select an alternative cout output pin. (6) note: do not use this pin as cout output if the ta0clk functionality is used on any other pin. select an alternative cout output pin. copyright ? 2014 ? 2015, texas instruments incorporated detailed description 93 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 6.11.23.4 port p1, p1.4 to p1.7, input/output with schmitt trigger pin schematic: see figure 6-1 . table 6-18. port p1 (p1.4 to p1.7) pin functions control bits and signals (1) pin name (p1.x) x function p1dir.x p1sel1.x p1sel0.x lcdsz p1.4/ucb0clk/uca0ste/ta1.0/sz 4 p1.4 (i/o) i: 0; o: 1 0 0 0 ucb0clk x (2) 0 1 0 uca0ste x (3) 1 0 0 ta1.cci0a 0 1 1 0 ta1.0 1 sz (4) x x x 1 p1.5/ucb0ste/uca0clk/ta0.0/sz 5 p1.5 (i/o) i: 0; o: 1 0 0 0 ucb0ste x (2) 0 1 0 uca0clk x (3) 1 0 0 ta0.cci0a 0 1 1 0 ta0.0 1 sz (4) x x x 1 p1.6/ucb0simo/ucb0sda/ta0.1/ 6 p1.6 (i/o) i: 0; o: 1 0 0 0 sz ucb0simo/ucb0sda x (2) 0 1 0 n/a 0 1 0 0 internally tied to dvss 1 ta0.cci1a 0 1 1 0 ta0.1 1 sz (4) x x x 1 p1.7/ucb0somi/ucb0scl/ta0.2/ 7 p1.7 (i/o) i: 0; o: 1 0 0 0 sz ucb0somi/ucb0scl x (2) 0 1 0 n/a 0 1 0 0 internally tied to dvss 1 ta0.cci2a 0 1 1 0 ta0.2 1 sz (4) x x x 1 (1) x = don ' t care (2) direction controlled by eusci_b0 module. (3) direction controlled by eusci_a0 module. (4) the associated lcd segment is package dependent. see the signal descriptions tables and pin diagrams figures. 94 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 6.11.23.5 port p2, p2.0 to p2.3, input/output with schmitt trigger pin schematic: see figure 6-1 . table 6-19. port p2 (p2.0 to p2.3) pin functions control bits and signals (1) pin name (p2.x) x function p2dir.x p2sel1.x p2sel0.x lcdsz p2.0/uca0simo/uca0txd/tb0.6/ 0 p2.0 (i/o) i: 0; o: 1 0 0 0 tb0clk/sz uca0simo/uca0txd x (2) 0 1 0 tb0.cci6b 0 1 0 0 tb0.6 1 tb0clk 0 1 1 0 internally tied to dvss 1 sz (3) x x x 1 p2.1/uca0somi/uca0rxd/tb0.5/ 1 p2.1 (i/o) i: 0; o: 1 0 0 0 dmae0/sz uca0somi/uca0rxd x (2) 0 1 0 tb0.cci5b 0 1 0 0 tb0.5 1 dma0e 0 1 1 0 internally tied to dvss 1 sz (3) x x x 1 p2.2/uca0clk/tb0.4/rtcclk/sz 2 p2.2 (i/o) i: 0; o: 1 0 0 0 uca0clk x (2) 0 1 0 tb0.cci4b 0 1 0 0 tb0.4 1 n/a 0 1 1 0 rtcclk 1 sz (3) x x x 1 p2.3/uca0ste/tb0outh/sz 3 p2.3 (i/o) i: 0; o: 1 0 0 0 uca0ste x (2) 0 1 0 tb0outh 0 1 0 0 internally tied to dvss 1 n/a 0 1 1 0 internally tied to dvss 1 sz (3) x x x 1 (1) x = don ' t care (2) direction controlled by eusci_a0 module. (3) the associated lcd segment is package dependent. see the signal descriptions tables and pin diagrams figures. copyright ? 2014 ? 2015, texas instruments incorporated detailed description 95 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 6.11.23.6 port p2, p2.4 to p2.7, input/output with schmitt trigger a. the inputs from several pins toward a module are ored together. note: functional representation only. 96 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 p2.4/tb0.3/com4/szp2.5/tb0.4/com5/sz p2.6/tb0.5/com6/sz p2.7/tb0.6/com7/sz p2sel1.x p2dir.x p2in.x from module 1 p2out.x 1 0 dvssdvcc 1 com4/5/6/7 pad logic sz lcdsz bus keeper direction0: input 1: output p2ren.x 0 1 0 01 0 1 1 p2sel0.x 0 1 0 01 0 1 1 from module 2 dvss to module 1 (a) to module 2 (a)
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 6-20. port p2 (p2.4 to p2.7) pin functions control bits and signals (1) pin name (p2.x) x function p2dir.x p2sel1.x p2sel0.x lcdsz p2.4/tb0.3/com4/sz 4 p2.4 (i/o) i: 0; o: 1 0 0 0 tb0.cci3a 0 0 1 0 tb0.3 1 n/a 0 1 0 0 internally tied to dvss 1 com4 x 1 1 0 sz (2) x x x 1 p2.5/tb0.4/com5/sz 5 p2.5 (i/o) i: 0; o: 1 0 0 0 tb0.cci4a 0 0 1 0 tb0.4 1 n/a 0 1 0 0 internally tied to dvss 1 com5 x 1 1 0 sz (2) x x x 1 p2.6/tb0.5/ esic1out/com6/sx 6 p2.6 (i/o) i: 0; o: 1 0 0 0 tb0.cci5a 0 0 1 0 tb0.5 1 n/a 0 1 0 0 esic1out 1 com6 x 1 1 0 sz (2) x x x 1 p2.7/tb0.6/ esic2out/com7/sx 7 p2.7 (i/o) i: 0; o: 1 0 0 0 tb0.cci6a 0 0 1 0 tb0.6 1 n/a 0 1 0 0 esic2out 1 com7 x 1 1 0 sz (2) x x x 1 (1) x = don ' t care (2) the associated lcd segment is package dependent. see the signal descriptions tables and pin diagrams figures. copyright ? 2014 ? 2015, texas instruments incorporated detailed description 97 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 6.11.23.7 port p3, p3.0 to p3.7, input/output with schmitt trigger pin schematic: see figure 6-1 . table 6-21. port p3 (p3.0 to p3.3) pin functions control bits and signals (1) pin name (p3.x) x function p3dir.x p3sel1.x p3sel0.x lcdsz p3.0/ucb1clk/sz 0 p3.0 (i/o) i: 0; o: 1 0 0 0 ucb1clk x (2) 0 1 0 n/a 0 1 0 0 internally tied to dvss 1 n/a 0 1 1 0 internally tied to dvss 1 sz (3) x x x 1 p3.1/ucb1simo/ucb1sda/sz 1 p3.1 (i/o) i: 0; o: 1 0 0 0 ucb1simo/ucb1sda x (2) 0 1 0 n/a 0 1 0 0 internally tied to dvss 1 n/a 0 1 1 0 internally tied to dvss 1 sz (3) x x x 1 p3.2/ucb1somi/ucb1scl/sz 2 p3.2 (i/o) i: 0; o: 1 0 0 0 ucb1somi/ucb1scl x (2) 0 1 0 n/a 0 1 0 0 internally tied to dvss 1 0 1 1 0 1 sz (3) x x x 1 p3.3/ta1.1/tb0clk/sz 3 p3.3 (i/o) i: 0; o: 1 0 0 0 n/a 0 0 1 0 internally tied to dvss 1 ta1.cci1a 0 1 0 0 ta1.1 1 tb0clk 0 1 1 0 internally tied to dvss 1 sz (3) x x x 1 (1) x = don ' t care (2) direction controlled by eusci_b1 module. (3) the associated lcd segment is package dependent. see the signal descriptions tables and pin diagrams figures. 98 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 6-22. port p3 (p3.4 to p3.7) pin functions control bits and signals (1) pin name (p3.x) x function p3dir.x p3sel1.x p3sel0.x lcdsz p3.4/uca1simo/uca1txd/tb0.0/ 4 p3.4 (i/o) i: 0; o: 1 0 0 0 sz uca1simo/uca1txd x (2) 0 1 0 tb0cci0a 0 1 0 0 tb0.0 1 n/a 0 1 1 0 internally tied to dvss 1 sz (3) x x x 1 p3.5/uca1somi/uca1rxd/tb0.1/ 5 p3.5 (i/o) i: 0; o: 1 0 0 0 sz uca1somi/uca1rxd x (2) 0 1 0 tb0cci1a 0 1 0 0 tb0.1 1 n/a 0 1 1 0 internally tied to dvss 1 sz (3) x x x 1 p3.6/uca1clk/tb0.2/sz 6 p3.6 (i/o) i: 0; o: 1 0 0 0 uca1clk x (2) 0 1 0 tb0cci2a 0 1 0 0 tb0.2 1 n/a 0 1 1 0 internally tied to dvss 1 sz (3) x x x 1 p3.7/uca1ste/tb0.3/sz 7 p3.7 (i/o) i: 0; o: 1 0 0 0 uca1ste x (2) 0 1 0 tb0cci3b 0 1 0 0 tb0.3 1 n/a 0 1 1 0 internally tied to dvss 1 sz (3) x x x 1 (1) x = don ' t care (2) direction controlled by eusci_a1 module. (3) the associated lcd segment is package dependent. see the signal descriptions tables and pin diagrams figures. copyright ? 2014 ? 2015, texas instruments incorporated detailed description 99 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 6.11.23.8 port p4, p4.0 to p4.7, input/output with schmitt trigger pin schematic: see figure 6-1 . table 6-23. port p4 (p4.0 to p4.3) pin functions control bits and signals (1) pin name (p4.x) x function p4dir.x p4sel1.x p4sel0.x lcdsz p4.0/ucb1simo/ucb1sda/mclk/ 0 p4.0 (i/o) i: 0; o: 1 0 0 0 sz n/a 0 0 1 0 internally tied to dvss 1 ucb1simo/ucb1sda x (2) 1 0 0 n/a 0 1 1 0 mclk 1 sz (3) x x x 1 p4.1/ucb1somi/ucb1scl/aclk/ 1 p4.1 (i/o) i: 0; o: 1 0 0 0 sz n/a 0 0 1 0 internally tied to dvss 1 ucb1somi/ucb1scl x (2) 1 0 0 n/a 0 1 1 0 aclk 1 sz (3) x x x 1 p4.2/uca0simo/uca0txd/ 2 p4.2 (i/o) i: 0; o: 1 0 0 0 ucb1clk/sz uca0simo/uca0txd x (4) 0 1 0 ucb1clk x (2) 1 0 0 n/a 0 1 1 0 internally tied to dvss 1 sz (3) x x x 1 p4.3/uca0somi/uca0rxd/ 3 p4.3 (i/o) i: 0; o: 1 0 0 0 ucb1ste/sz uca0somi/uca0rxd x (4) 0 1 0 ucb1ste x (2) 1 0 0 n/a 0 1 1 0 internally tied to dvss 1 sz (3) x x x 1 (1) x = don ' t care (2) direction controlled by eusci_b1 module. (3) the associated lcd segment is package dependent. see the signal descriptions tables and pin diagrams figures. (4) direction controlled by eusci_a0 module. 100 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 6-24. port p4 (p4.4 to p4.7) pin functions control bits and signals (1) pin name (p4.x) x function p4dir.x p4sel1.x p4sel0.x lcdsz p4.4/ucb1ste/ta1clk/sz 4 p4.4 (i/o) i: 0; o: 1 0 0 0 n/a 0 0 1 0 internally tied to dvss 1 ucb1ste x (2) 1 0 0 ta1clk 0 1 1 0 internally tied to dvss 1 sz (3) x x x 1 p4.5/ucb1clk/ta1.0/sz 5 p4.5 (i/o) i: 0; o: 1 0 0 0 n/a 0 0 1 0 internally tied to dvss 1 ucb1clk x (2) 1 0 0 ta1cci0a 0 1 1 0 ta1.0 1 sz (3) x x x 1 p4.6/ucb1simo/ucb1sda/ta1.1/ 6 p4.6 (i/o) i: 0; o: 1 0 0 0 sz n/a 0 0 1 0 internally tied to dvss 1 ucb1simo/ucb1sda x (2) 1 0 0 ta1cci1a 0 1 1 0 ta1.1 1 sz (3) x x x 1 p4.7/ucb1somi/ucb1scl/ta1.2/ 7 p4.7 (i/o) i: 0; o: 1 0 0 0 sz n/a 0 0 1 0 internally tied to dvss 1 ucb1somi/ucb1scl x (2) 1 0 0 ta1cci2a 0 1 1 0 ta1.2 1 sz (3) x x x 1 (1) x = don ' t care (2) direction controlled by eusci_b1 module. (3) the associated lcd segment is package dependent. see the signal descriptions tables and pin diagrams figures. copyright ? 2014 ? 2015, texas instruments incorporated detailed description 101 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 6.11.23.9 port p5, p5.0 to p5.7, input/output with schmitt trigger pin schematic: see figure 6-1 . table 6-25. port p5 (p5.0 to p5.3) pin functions control bits and signals (1) pin name (p5.x) x function p5dir.x p5sel1.x p5sel0.x lcdsz p5.0/ta1.1/mclk/sz 0 p5.0 (i/o) i: 0; o: 1 0 0 0 ta1cci1a 0 0 1 0 ta1.1 1 n/a 0 1 0 0 internally tied to dvss 1 n/a 0 1 1 0 mclk 1 sz (2) x x x 1 p5.1/ta1.2/sz 1 p5.1 (i/o) i: 0; o: 1 0 0 0 ta1cci2a 0 0 1 0 ta1.2 1 n/a 0 1 0 0 internally tied to dvss 1 n/a 0 1 1 0 n/a 1 sz (2) x x x 1 p5.2/ta1.0/ta1clk/aclk/sz 2 p5.2 (i/o) i: 0; o: 1 0 0 0 ta1cci0b 0 0 1 0 ta1.0 1 ta1clk 0 1 0 0 internally tied to dvss 1 n/a 0 1 1 0 aclk 1 sz (2) x x x 1 p5.3/ucb1ste/sz 3 p5.3 (i/o) i: 0; o: 1 0 0 0 n/a 0 0 1 0 internally tied to dvss 1 ucb1ste x (3) 1 0 0 n/a 0 1 1 0 internally tied to dvss 1 sz (2) x x x 1 (1) x = don ' t care (2) the associated lcd segment is package dependent. see the signal descriptions tables and pin diagrams figures. (3) direction controlled by eusci_b1 module. 102 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 6-26. port p5 (p5.4 to p5.7) pin functions control bits and signals (1) pin name (p5.x) x function p5dir.x p5sel1.x p5sel0.x lcdsz p5.4/uca1simo/uca1txd/sz 4 p5.4 (i/o) i: 0; o: 1 0 0 0 uca1simo/uca1txd x (2) 0 1 0 n/a 0 1 0 0 internally tied to dvss 1 n/a 0 1 1 0 internally tied to dvss 1 sz (3) x x x 1 p5.5/uca1somi/uca1rxd/sz 5 p5.5 (i/o) i: 0; o: 1 0 0 0 uca1somi/uca1rxd x (2) 0 1 0 n/a 0 1 0 0 internally tied to dvss 1 n/a 0 1 1 0 internally tied to dvss 1 sz (3) x x x 1 p5.6/uca1clk/sz 6 p5.6 (i/o) i: 0; o: 1 0 0 0 uca1clk x (2) 0 1 0 n/a 0 1 0 0 internally tied to dvss 1 n/a 0 1 1 0 internally tied to dvss 1 sz (3) x x x 1 p5.7/uca1ste/tb0clk/sz 7 p5.7 (i/o) i: 0; o: 1 0 0 0 uca1ste x (2) 0 1 0 n/a 0 1 0 0 internally tied to dvss 1 tb0clk 0 1 1 0 internally tied to dvss 1 sz (3) x x x 1 (1) x = don ' t care (2) direction controlled by eusci_a1 module. (3) the associated lcd segment is package dependent. see the signal descriptions tables and pin diagrams figures. copyright ? 2014 ? 2015, texas instruments incorporated detailed description 103 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 6.11.23.10 port p6, p6.0 to p6.7, input/output with schmitt trigger a. the inputs from several pins toward a module are ored together. note: functional representation only. 104 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 p6.0/r23p6.1/r13/lcdref p6.2/cout/r03 p6.3/com0 p6.4/tb0.0/com1 p6.5/tb0.1/com2 p6.6/tb0.2/com3 p6sel1.x p6dir.x p6in.x from module 1 p6out.x 1 0 dvssdvcc 1 to/from lcd module pad logic bus keeper direction0: input 1: output p6ren.x 0 1 0 01 0 1 1 p6sel0.x 0 1 0 01 0 1 1 from module 2 dvss to module 1 (a) to module 2 (a)
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 6-27. port p6 (p6.0 to p6.2) pin functions control bits and signals (1) pin name (p6.x) x function p6dir.x p6sel1.x p6sel0.x lcdsz p6.0/r23 0 p6.0 (i/o) i: 0; o: 1 0 0 - n/a 0 0 1 - internally tied to dvss 1 n/a 0 1 0 - internally tied to dvss 1 r23 (2) x 1 1 - p6.1/r13/lcdref 1 p6.1 (i/o) i: 0; o: 1 0 0 - n/a 0 0 1 - internally tied to dvss 1 n/a 0 1 0 - internally tied to dvss 1 r13/lcdref (2) x 1 1 - p6.2/cout/r03 2 p6.2 (i/o) i: 0; o: 1 0 0 - n/a 0 0 1 - cout 1 n/a 0 1 0 - internally tied to dvss 1 r03 (2) x 1 1 - (1) x = don ' t care (2) setting p6sel1.x and p6sel0.x disables the output driver and the input schmitt trigger to prevent parasitic cross currents when applying analog signals. copyright ? 2014 ? 2015, texas instruments incorporated detailed description 105 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com table 6-28. port p6 (p6.3 to p6.6) pin functions control bits and signals (1) pin name (p6.x) x function p6dir.x p6sel1.x p6sel0.x lcdsz p6.3/com0 3 p6.3 (i/o) i: 0; o: 1 0 0 - n/a 0 0 1 - internally tied to dvss 1 n/a 0 1 0 - internally tied to dvss 1 com0 (2) x 1 1 - p6.4/tb0.0/com1 4 p6.4 (i/o) i: 0; o: 1 0 0 - tb0cci0b 0 0 1 - tb0.0 1 n/a 0 1 0 - internally tied to dvss 1 com1 (2) x 1 1 - p6.5/tb0.1/com2 5 p6.5 (i/o) i: 0; o: 1 0 0 - tb0cci1a 0 0 1 - tb0.1 1 n/a 0 1 0 - internally tied to dvss 1 com2 (2) x 1 1 - p6.6/tb0.2/com3 6 p6.6 (i/o) i: 0; o: 1 0 0 - tb0cci2a 0 0 1 - tb0.2 1 n/a 0 1 0 - internally tied to dvss 1 com3 (2) x 1 1 - (1) x = don ' t care (2) setting p6sel1.x and p6sel0.x disables the output driver and the input schmitt trigger to prevent parasitic cross currents when applying analog signals. 106 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 6.11.23.11 port p6, p6.7, input/output with schmitt trigger pin schematic: see figure 6-1 . table 6-29. port p6 (p6.7) pin functions control bits and signals (1) pin name (p6.x) x function p6dir.x p6sel1.x p6sel0.x lcdsz p6.7/ta0clk/sz 7 p6.7 (i/o) i: 0; o: 1 0 0 0 ta0clk 0 0 1 0 internally tied to dvss 1 n/a 0 1 0 0 internally tied to dvss 1 n/a 0 1 1 0 internally tied to dvss 1 sz (2) x x x 1 (1) x = don ' t care (2) the associated lcd segment is package dependent. see the signal descriptions tables and pin diagrams figures. copyright ? 2014 ? 2015, texas instruments incorporated detailed description 107 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 6.11.23.12 port p7, p7.0 to p7.7, input/output with schmitt trigger pin schematic: see figure 6-1 . table 6-30. port p7 (p7.0 to p7.3) pin functions control bits and signals (1) pin name (p7.x) x function p7dir.x p7sel1.x p7sel0.x lcdsz p7.0/ta0clk/sz 0 p7.0 (i/o) i: 0; o: 1 0 0 0 ta0clk 0 0 1 0 internally tied to dvss 1 n/a 0 1 0 0 internally tied to dvss 1 n/a 0 1 1 0 internally tied to dvss 1 sz (2) x x x 1 p7.1/ta0.0/sz 1 p7.1 (i/o) i: 0; o: 1 0 0 0 ta0cci0b 0 0 1 0 ta0.0 1 n/a 0 1 0 0 internally tied to dvss 1 n/a 0 1 1 0 aclk 1 sz (2) x x x 1 p7.2/ta0.1/sz 2 p7.2 (i/o) i: 0; o: 1 0 0 0 ta0cci1a 0 0 1 0 ta0.1 1 n/a 0 1 0 0 internally tied to dvss 1 n/a 0 1 1 0 n/a 1 sz (2) x x x 1 p7.3/ta0.2/sz 3 p7.3 (i/o) i: 0; o: 1 0 0 0 ta0cci2a 0 0 1 0 ta0.2 1 n/a 0 1 0 0 internally tied to dvss 1 n/a 0 1 1 0 internally tied to dvss 1 sz (2) x x x 1 (1) x = don ' t care (2) the associated lcd segment is package dependent. see the signal descriptions tables and pin diagrams figures. 108 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 6-31. port p7 (p7.4 to p7.7) pin functions control bits and signals (1) pin name (p7.x) x function p7dir.x p7sel1.x p7sel0.x lcdsz p7.4/smclk/sz 4 p7.4 (i/o) i: 0; o: 1 0 0 0 n/a 0 0 1 0 internally tied to dvss 1 n/a 0 1 0 0 internally tied to dvss 1 n/a 0 1 1 0 smclk 1 sz (2) x x x 1 p7.5/ta0.2/sz 5 p7.5 (i/o) i: 0; o: 1 0 0 0 ta0cci2a 0 0 1 0 ta0.2 1 n/a 0 1 0 0 internally tied to dvss 1 n/a 0 1 1 0 internally tied to dvss 1 sz (2) x x x 1 p7.6/ta0.1/sz 6 p7.6 (i/o) i: 0; o: 1 0 0 0 ta0cci1a 0 0 1 0 ta0.1 1 n/a 0 1 0 0 internally tied to dvss 1 n/a 0 1 1 0 internally tied to dvss 1 sz (2) x x x 1 p7.7/ta1.2/tb0outh/sz 7 p7.7 (i/o) i: 0; o: 1 0 0 0 n/a 0 0 1 0 internally tied to dvss 1 ta1.cci2a 0 1 0 0 ta1.2 1 tb0outh 0 1 1 0 internally tied to dvss 1 sz (2) x x x 1 (1) x = don ' t care (2) the associated lcd segment is package dependent. see the signal descriptions tables and pin diagrams figures. copyright ? 2014 ? 2015, texas instruments incorporated detailed description 109 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 6.11.23.13 port p8, p8.0 to p8.3, input/output with schmitt trigger pin schematic: see figure 6-1 . table 6-32. port p8 (p8.0 to p8.3) pin functions control bits and signals (1) pin name (p8.x) x function p8dir.x p8sel1.x p8sel0.x lcdsz p8.0/rtcclk/sz 0 p8.0 (i/o) i: 0; o: 1 0 0 0 n/a 0 0 1 0 internally tied to dvss 1 n/a 0 1 0 0 internally tied to dvss 1 n/a 0 1 1 0 rtcclk 1 sz (2) x x x 1 p8.1/dmae0/sz 1 p8.1 (i/o) i: 0; o: 1 0 0 0 n/a 0 0 1 0 internally tied to dvss 1 n/a 0 1 0 0 internally tied to dvss 1 dma0e 0 1 1 0 internally tied to dvss 1 sz (2) x x x 1 p8.2/sz 2 p8.2 (i/o) i: 0; o: 1 0 0 0 n/a 0 0 1 0 internally tied to dvss 1 n/a 0 1 0 0 internally tied to dvss 1 n/a 0 1 1 0 internally tied to dvss 1 sz (2) x x x 1 p8.3/mclk/sz 3 p8.3 (i/o) i: 0; o: 1 0 0 0 n/a 0 0 1 0 internally tied to dvss 1 n/a 0 1 0 0 internally tied to dvss 1 n/a 0 1 1 0 mclk 1 sz (2) x x x 1 (1) x = don ' t care (2) the associated lcd segment is package dependent. see the signal descriptions tables and pin diagrams figures. 110 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 6.11.23.14 port p8, p8.4 to p8.7, input/output with schmitt trigger note: functional representation only. copyright ? 2014 ? 2015, texas instruments incorporated detailed description 111 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 p8.4/a7/c7p8.5/a6/c6 p8.6/a5/c5 p8.7/a4/c4 p8sel1.x p8dir.x p8in.x dvss p8out.x 1 0 dvssdvcc 1 to comparator from comparator pad logic to adc from adc bus keeper direction0: input 1: output cepd.x p8ren.x 0 1 0 01 0 1 1 p8sel0.x 0 1 0 01 0 1 1 dvss dvss
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com table 6-33. port p8 (p8.4 to p8.7) pin functions control bits and signals (1) pin name (p8.x) x function p8dir.x p8sel1.x p8sel0.x p8.4/a7/c7 4 p8.4 (i/o) i: 0; o: 1 0 0 n/a 0 0 1 internally tied to dvss 1 n/a 0 1 0 internally tied to dvss 1 a7/c7 (2) (3) x 1 1 p8.5/a6/c6 5 p8.5 (i/o) i: 0; o: 1 0 0 n/a 0 0 1 internally tied to dvss 1 n/a 0 1 0 internally tied to dvss 1 a6/c6 (2) (3) x 1 1 p8.6/a5/c5 6 p8.6 (i/o) i: 0; o: 1 0 0 n/a 0 0 1 internally tied to dvss 1 n/a 0 1 0 internally tied to dvss 1 a5/c5 (2) (3) x 1 1 p8.7/a4/c4 7 p8.7 (i/o) i: 0; o: 1 0 0 n/a 0 0 1 internally tied to dvss 1 n/a 0 1 0 internally tied to dvss 1 a4/c4 (2) (3) x 1 1 (1) x = don ' t care (2) setting p8sel1.x and p8sel0.x disables the output driver and the input schmitt trigger to prevent parasitic cross currents when applying analog signals. (3) setting the cepd.x bit of the comparator disables the output driver and the input schmitt trigger to prevent parasitic cross currents when applying analog signals. selecting the cx input pin to the comparator multiplexer with the input select bits in the comparator module automatically disables output driver and input buffer for that pin, regardless of the state of the associated cepd.x bit. 112 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 6.11.23.15 port p9, p9.0 to p9.3, input/output with schmitt trigger note: functional representation only. copyright ? 2014 ? 2015, texas instruments incorporated detailed description 113 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 p9.0/esich0/esitest0/a8/c8p9.1/esich1/esitest1/a9/c9 p9.2/esich2/esitest2/a10/c10 p9.3/esich3/esitest3/a11/c11 p9sel1.x p9dir.x p9in.x dvss p9out.x 1 0 dvssdvcc 1 to comparator from comparator pad logic to adc to esi esitestx from adc bus keeper direction0: input 1: output cepd.x p9ren.x 0 1 0 01 0 1 1 p9sel0.x 0 1 0 01 0 1 1 dvss dvss
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com table 6-34. port p9 (p9.0 to p9.3) pin functions control bits and signals (1) pin name (p9.x) x function p9dir.x p9sel1.x p9sel0.x p9.0/ esich0/esitest0/a8/c8 0 p9.0 (i/o) i: 0; o: 1 0 0 n/a 0 0 1 internally tied to dvss 1 esitest0 (2) x 1 0 esich0/a8/c8 (2) (3) (4) x 1 1 p9.1/ esich1/esitest1/a9/c9 1 p9.1 (i/o) i: 0; o: 1 0 0 n/a 0 0 1 internally tied to dvss 1 esitest1 (2) x 1 0 esich1/a9/c9 (2) (3) (4) x 1 1 p9.2/ esich2/esitest2/a10/c10 2 p9.2 (i/o) i: 0; o: 1 0 0 n/a 0 0 1 internally tied to dvss 1 esitest2 (2) x 1 0 esich2/a10/c10 (2) (3) (4) x 1 1 p9.3/ esich3/esitest3/a11/c11 3 p9.3 (i/o) i: 0; o: 1 0 0 n/a 0 0 1 internally tied to dvss 1 esitest3 (2) x 1 0 esich3/a11/c11 (2) (3) (4) x 1 1 (1) x = don ' t care (2) setting p9sel1.x disables the output driver and the input schmitt trigger to prevent parasitic cross currents when applying analog signals. (3) setting the cepd.x bit of the comparator disables the output driver and the input schmitt trigger to prevent parasitic cross currents when applying analog signals. selecting the cx input pin to the comparator multiplexer with the input select bits in the comparator module automatically disables output driver and input buffer for that pin, regardless of the state of the associated cepd.x bit. (4) depending on the configuration of the esi module other esichx pins are stimulated as well and thus should have the input schmitt triggers disabled (with p9sel1.x = 1) and cannot be used as digital i/o, adc or comparator inputs. 114 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 6.11.23.16 port p9, p9.4 to p9.7, input/output with schmitt trigger note: functional representation only. copyright ? 2014 ? 2015, texas instruments incorporated detailed description 115 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 p9.4/esici0/a12/c12p9.5/esici1/a13/c13 p9.6/esici2/a14/c14 p9.7/esici3/a15/c15 p9sel1.x p9dir.x p9in.x dvss p9out.x 1 0 dvssdvcc 1 to comparator from comparator pad logic to adc to esi from adc bus keeper direction0: input 1: output cepd.x p9ren.x 0 1 0 01 0 1 1 p9sel0.x 0 1 0 01 0 1 1 dvss dvss
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com table 6-35. port p9 (p9.4 to p9.7) pin functions control bits and signals (1) pin name (p9.x) x function p9dir.x p9sel1.x p9sel0.x p9.4/ esici0/a12/c12 4 p9.4 (i/o) i: 0; o: 1 0 0 n/a 0 0 1 internally tied to dvss 1 n/a 0 1 0 internally tied to dvss 1 esici0/a12/c12 (2) (3) (4) x 1 1 p9.5/ esici1/a13/c13 5 p9.5 (i/o) i: 0; o: 1 0 0 n/a 0 0 1 internally tied to dvss 1 n/a 0 1 0 internally tied to dvss 1 esici1/a13/c13 (2) (3) (4) x 1 1 p9.6/ esici2/a14/c14 6 p9.6 (i/o) i: 0; o: 1 0 0 n/a 0 0 1 internally tied to dvss 1 n/a 0 1 0 internally tied to dvss 1 esici2/a14/c14 (2) (3) (4) x 1 1 p9.7/ esici3/a15/c15 7 p9.7 (i/o) i: 0; o: 1 0 0 n/a 0 0 1 internally tied to dvss 1 n/a 0 1 0 internally tied to dvss 1 esici3/a15/c15 (2) (3) (4) x 1 1 (1) x = don ' t care (2) setting p9sel1.x and p9sel0.x disables the output driver and the input schmitt trigger to prevent parasitic cross currents when applying analog signals. (3) setting the cepd.x bit of the comparator disables the output driver and the input schmitt trigger to prevent parasitic cross currents when applying analog signals. selecting the cx input pin to the comparator multiplexer with the input select bits in the comparator module automatically disables output driver and input buffer for that pin, regardless of the state of the associated cepd.x bit. (4) depending on the configuration of the esi module, other esici2/ pins are used, and thus should have the input schmitt triggers disabled (with p9sel1.x = 1 and p9sel0.x = 1) and cannot be used as digital i/o, adc, or comparator inputs. 116 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 6.11.23.17 port p10, p10.0 to p10.2, input/output with schmitt trigger pin schematic: see figure 6-1 . table 6-36. port p10 (p10.0 to p10.2) pin functions control bits and signals (1) pin name (p10.x) x function p10dir.x p10sel1.x p10sel0.x lcdsz p10.0/smclk/sz 0 p10.0 (i/o) i: 0; o: 1 0 0 0 n/a 0 0 1 0 internally tied to dvss 1 n/a 0 1 0 0 internally tied to dvss 1 n/a 0 1 1 0 smclk 1 sz (2) x x x 1 p10.1/ta0.0/sz 1 p10.1 (i/o) i: 0; o: 1 0 0 0 ta0.cci0b 0 0 1 0 ta0.0 1 n/a 0 1 0 0 internally tied to dvss 1 n/a 0 1 1 0 internally tied to dvss 1 sz (2) x x x 1 p10.2/ta1.0/smclk/sz 2 p10.2 (i/o) i: 0; o: 1 0 0 0 ta1.cci0b 0 0 1 0 ta1.0 1 n/a 0 1 0 0 internally tied to dvss 1 n/a 0 1 1 0 smclk 1 sz (2) x x x 1 (1) x = don ' t care (2) the associated lcd segment is package dependent. see the signal descriptions tables and pin diagrams figures. copyright ? 2014 ? 2015, texas instruments incorporated detailed description 117 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 6.11.23.18 port pj, pj.4 and pj.5 input/output with schmitt trigger note: functional representation only. 118 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 pj.4/lfxin pjsel1.4 pjdir.4 pjin.4 en to modules dvss pjout.4 1 0 dvssdvcc 1 d to lfxt xin pad logic bus keeper direction0: input 1: output pjren.4 0 1 0 01 0 1 1 pjsel0.4 0 1 0 01 0 1 1 dvss dvss
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 note: functional representation only. copyright ? 2014 ? 2015, texas instruments incorporated detailed description 119 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 pj.5/lfxout pjsel1.5 pjdir.5 pjin.5 en to modules dvss pjout.5 1 0 dvssdvcc 1 d to lfxt xout pad logic bus keeper direction0: input 1: output pjren.5 0 1 0 01 0 1 1 pjsel0.5 0 1 0 01 0 1 1 dvss dvss pjsel1.4 pjsel0.4 lfxtbypass
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com table 6-37. port pj (pj.4 and pj.5) pin functions control bits and signals (1) pin name (pj.x) x function lfxt pjdir.x pjsel1.5 pjsel0.5 pjsel1.4 pjsel0.4 bypass pj.4/lfxin 4 pj.4 (i/o) i: 0; o: 1 x x 0 0 x n/a 0 x x 1 x x internally tied to dvss 1 lfxin crystal mode (2) x x x 0 1 0 lfxin bypass mode (2) x x x 0 1 1 pj.5/lfxout 5 0 0 0 pj.5 (i/o) i: 0; o: 1 0 0 1 x x x 1 (3) 0 0 0 n/a 0 see (4) see (4) 1 x x x 1 (3) 0 0 0 internally tied to dvss 1 see (4) see (4) 1 x x x 1 (3) lfxout crystal mode (2) x x x 0 1 0 (1) x = don ' t care (2) setting pjsel1.4 = 0 and pjsel0.4 = 1 causes the general-purpose i/o to be disabled. when lfxtbypass = 0, pj.4 and pj.5 are configured for crystal operation and pjsel1.5 and pjsel0.5 are do not care. when lfxtbypass = 1, pj.4 is configured for bypass operation and pj.5 is configured as general-purpose i/o. (3) when pj.4 is configured in bypass mode, pj.5 is configured as general-purpose i/o. (4) with pjsel0.5 = 1 or pjsel1.5 =1 the general-purpose i/o functionality is disabled. no input function is available. configured as output the pin will be actively pulled to zero. 120 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 6.11.23.19 port pj, pj.6 and pj.7 input/output with schmitt trigger note: functional representation only. copyright ? 2014 ? 2015, texas instruments incorporated detailed description 121 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 pj.6/hfxin pjsel1.6 pjdir.6 pjin.6 en to modules dvss pjout.6 1 0 dvssdvcc 1 d to hfxt xin pad logic bus keeper direction0: input 1: output pjren.6 0 1 0 01 0 1 1 pjsel0.6 0 1 0 01 0 1 1 dvss dvss
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com note: functional representation only. 122 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 pj.7/hfxout pjsel1.7 pjdir.7 pjin.7 en to modules dvss pjout.7 1 0 dvssdvcc 1 d to hfxt xout pad logic bus keeper direction0: input 1: output pjren.7 0 1 0 01 0 1 1 pjsel0.7 0 1 0 01 0 1 1 dvss dvss pjsel1.6 hfxtbypass pjsel0.6
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 6-38. port pj (pj.6 and pj.7) pin functions control bits and signals (1) pin name (pj.x) x function hfxt pjdir.x pjsel1.7 pjsel0.7 pjsel1.6 pjsel0.6 bypass pj.6/hfxin 6 pj.6 (i/o) i: 0; o: 1 x x 0 0 x n/a 0 x x 1 x x internally tied to dvss 1 hfxin crystal mode (2) x x x 0 1 0 hfxin bypass mode (2) x x x 0 1 1 pj.7/hfxout 5 0 0 0 pj.7 (i/o) i: 0; o: 1 0 0 1 x x x 1 (3) 0 0 0 n/a 0 see (4) see (4) 1 x x x 1 (3) 0 0 0 internally tied to dvss 1 see (4) see (4) 1 x x x 1 (3) hfxout crystal mode (2) x x x 0 1 0 (1) x = don ' t care (2) setting pjsel1.6 = 0 and pjsel0.6 = 1 causes the general-purpose i/o to be disabled. when hfxtbypass = 0, pj.6 and pj.7 are configured for crystal operation and pjsel1.6 and pjsel0.7 are do not care. when hfxtbypass = 1, pj.6 is configured for bypass operation and pj.7 is configured as general-purpose i/o. (3) when pj.6 is configured in bypass mode, pj.7 is configured as general-purpose i/o. (4) with pjsel0.7 = 1 or pjsel1.7 =1 the general-purpose i/o functionality is disabled. no input function is available. configured as output the pin will be actively pulled to zero. copyright ? 2014 ? 2015, texas instruments incorporated detailed description 123 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 6.11.23.20 port j, j.0 to j.3 jtag pins tdo, tms, tck, tdi/tclk, input/output with schmitt trigger note: functional representation only. 124 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 pj.0/tdo/tb0outh/ smclk srscg1 pj.1/tdi/tclk/mclk/ srscg0 pj.2/tms/aclk/ sroscoff pj.3/tck/cout/ srcpuoff pjsel1.x pjdir.x pjin.x en to modules and jtag from module 1 pjout.x 1 0 dvssdvcc 1 d pad logic bus keeper direction0: input 1: output pjren.x 0 1 0 01 0 1 1 pjsel0.x 0 1 0 01 0 1 1 from status register (sr) dvss dvss 0 1 0 1 jtag enable from jtag from jtag
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 6-39. port pj (pj.0 to pj.3) pin functions control bits/ signals (1) pin name (pj.x) x function pjdir.x pjsel1.x pjsel0.x pj.0/tdo/tb0outh/ 0 pj.0 (i/o) (2) i: 0; o: 1 0 0 smclk/srscg1 tdo (3) x x x tb0outh 0 0 1 smclk (4) 1 n/a 0 1 0 cpu status register bit scg1 1 n/a 0 1 1 internally tied to dvss 1 pj.1/tdi/tclk/mclk/ 1 pj.1 (i/o) (2) i: 0; o: 1 0 0 srscg0 tdi/tclk (3) (5) x x x n/a 0 0 1 mclk 1 n/a 0 1 0 cpu status register bit scg0 1 n/a 0 1 1 internally tied to dvss 1 pj.2/tms/aclk/ 2 pj.2 (i/o) (2) i: 0; o: 1 0 0 sroscoff tms (3) (5) x x x n/a 0 0 1 aclk 1 n/a 0 1 0 cpu status register bit oscoff 1 n/a 0 1 1 internally tied to dvss 1 pj.3/tck/cout/ 3 pj.3 (i/o) (2) i: 0; o: 1 0 0 srcpuoff tck (3) (5) x x x n/a 0 0 1 cout 1 n/a 0 1 0 cpu status register bit cpuoff 1 n/a 0 1 1 internally tied to dvss 1 (1) x = don ' t care (2) default condition (3) the pin direction is controlled by the jtag module. jtag mode selection is made via the sys module or by the spybiwire four wire entry sequence. neither pjsel1.x and pjsel0.x nor cepd.x bits have an effect in these cases. (4) note: do not use this pin as smclk output if the tb0outh functionality is used on any other pin. select an alternative smclk output pin. (5) in jtag mode, pullups are activated automatically on tms, tck, and tdi/tclk. pjren.x are do not care. copyright ? 2014 ? 2015, texas instruments incorporated detailed description 125 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 6.12 device descriptors (tlv) table 6-41 lists the contents of the device descriptor tag-length-value (tlv) structure for each device type. table 6-40 summarizes the device ids. table 6-40. device id device id device 01a05h 01a04h msp430fr6889 081h 0c0h msp430fr6888 081h 0bfh msp430fr6887 081h 0beh msp430fr5889 081h 0c3h msp430fr5888 081h 0c2h msp430fr5887 081h 0c1h msp430fr68891 081h 0c0h msp430fr58891 081h 0c3h 126 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 6-41. device descriptor table (1) msp430frxxxx (uart bsl) msp430frxxxx1 (i 2 c bsl) description address value address value info block info length 01a00h 06h 01a00h 06h crc length 01a01h 06h 01a01h 06h 01a02h per unit 01a02h per unit crc value 01a03h per unit 01a03h per unit 01a04h 01a04h device id see table 6-40 see table 6-40 01a05h 01a05h hardware revision 01a06h per unit 01a06h per unit firmware revision 01a07h per unit 01a07h per unit die record die record tag 01a08h 08h 01a08h 08h die record length 01a09h 0ah 01a09h 0ah 01a0ah per unit 01a0ah per unit 01a0bh per unit 01a0bh per unit lot/wafer id 01a0ch per unit 01a0ch per unit 01a0dh per unit 01a0dh per unit 01a0eh per unit 01a0eh per unit die x position 01a0fh per unit 01a0fh per unit 01a10h per unit 01a10h per unit die y position 01a11h per unit 01a11h per unit 01a12h per unit 01a12h per unit test results 01a13h per unit 01a13h per unit adc12b adc12b calibration tag 01a14h 11h 01a14h 11h calibration adc12b calibration length 01a15h 10h 01a15h 10h 01a16h per unit 01a16h per unit adc gain factor (2) 01a17h per unit 01a17h per unit 01a18h per unit 01a18h per unit adc offset (3) 01a19h per unit 01a19h per unit 01a1ah per unit 01a1ah per unit adc 1.2-v reference temp. sensor 30 c 01a1bh per unit 01a1bh per unit 01a1ch per unit 01a1ch per unit adc 1.2-v reference temp. sensor 85 c 01a1dh per unit 01a1dh per unit 01a1eh per unit 01a1eh per unit adc 2.0-v reference temp. sensor 30 c 01a1fh per unit 01a1fh per unit 01a20h per unit 01a20h per unit adc 2.0-v reference temp. sensor 85 c 01a21h per unit 01a21h per unit 01a22h per unit 01a22h per unit adc 2.5-v reference temp. sensor 30 c 01a23h per unit 01a23h per unit 01a24h per unit 01a24h per unit adc 2.5-v reference temp. sensor 85 c 01a25h per unit 01a25h per unit ref calibration ref calibration tag 01a26h 12h 01a26h 12h ref calibration length 01a27h 06h 01a27h 06h 01a28h per unit 01a28h per unit ref 1.2-v reference 01a29h per unit 01a29h per unit (1) na = not applicable per unit = content can differ from device to device (2) adc gain: the gain correction factor is measured using the internal voltage reference with refout=0. other settings (for example, with refout = 1) can result in different correction factors. (3) adc offset: the offset correction factor is measured using the internal 2.5-v reference. copyright ? 2014 ? 2015, texas instruments incorporated detailed description 127 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com table 6-41. device descriptor table (1) (continued) msp430frxxxx (uart bsl) msp430frxxxx1 (i 2 c bsl) description address value address value 01a2ah per unit 01a2ah per unit ref 2.0-v reference 01a2bh per unit 01a2bh per unit 01a2ch per unit 01a2ch per unit ref 2.5-v reference 01a2dh per unit 01a2dh per unit 128-bit random number random number 01a2eh 15h 01a2eh 15h tag random number length 01a2fh 10h 01a2fh 10h 01a30h per unit 01a30h per unit 01a31h per unit 01a31h per unit 01a32h per unit 01a32h per unit 01a33h per unit 01a33h per unit 01a34h per unit 01a34h per unit 01a35h per unit 01a35h per unit 01a36h per unit 01a36h per unit 01a37h per unit 01a37h per unit 128-bit random number (4) 01a38h per unit 01a38h per unit 01a39h per unit 01a39h per unit 01a3ah per unit 01a3ah per unit 01a3bh per unit 01a3bh per unit 01a3ch per unit 01a3ch per unit 01a3dh per unit 01a3dh per unit 01a3eh per unit 01a3eh per unit 01a3fh per unit 01a3fh per unit bsl configuration bsl tag 01a40h 1ch 01a40h 1ch bsl length 01a41h 02h 01a41h 02h bsl interface 01a42h 00h 01a42h 01h bsl interface 01a43h 00h 01a43h 48h configuration (4) 128-bit random number: the random number is generated during production test using the cryptgenrandom() function from microsoft ? . 128 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 6.13 memory table 6-42 shows the memory organization. table 6-42. memory organization (1) msp430frxxx9(1) msp430frxxx8(1) msp430frxxx7(1) memory (fram) total size 127kb 95kb 63kb main: interrupt vectors 00ffffh ? 00ff80h 00ffffh ? 00ff80h 00ffffh ? 00ff80h and signatures 023fffh ? 004400h 01bfffh ? 004400h 013fffh ? 004400h main: code memory sect 1 2kb 2kb 2kb ram 0023ffh ? 001c00h 0023ffh ? 001c00h 0023ffh ? 001c00h 256 b 256 b 256 b boot memory (rom) 001bffh ? 001b00h 001bffh ? 001b00h 001bffh ? 001b00h device descriptor info 256 b 256 b 256 b (tlv) 001affh ? 001a00h 001affh ? 001a00h 001affh ? 001a00h info a 128 b 128 b 128 b 0019ffh ? 001980h 0019ffh ? 001980h 0019ffh ? 001980h info b 128 b 128 b 128 b 00197fh ? 001900h 00197fh ? 001900h 00197fh ? 001900h information memory (fram) info c 128 b 128 b 128 b 0018ffh ? 001880h 0018ffh ? 001880h 0018ffh ? 001880h info d 128 b 128 b 128 b 00187fh ? 001800h 00187fh ? 001800h 00187fh ? 001800h bsl 3 512 b 512 b 512 b 0017ffh ? 001600h 0017ffh ? 001600h 0017ffh ? 001600h bsl 2 512 b 512 b 512 b 0015ffh ? 001400h 0015ffh ? 001400h 0015ffh ? 001400h bootstrap loader (bsl) memory (rom) bsl 1 512 b 512 b 512 b 0013ffh ? 001200h 0013ffh ? 001200h 0013ffh ? 001200h bsl 0 512 b 512 b 512 b 0011ffh ? 001000h 0011ffh ? 001000h 0011ffh ? 001000h size 4kb 4kb 4kb peripherals 000fffh ? 000020h 000fffh ? 000020h 000fffh ? 000020h size 26 b 26 b 26 b tiny ram 000001fh ? 000006h 000001fh ? 000006h 000001fh ? 000006h reserved size 6 b 6 b 6 b (read only) 000005h ? 000000h 000005h ? 000000h 000005h ? 000000h (1) all address space not listed is considered vacant memory. copyright ? 2014 ? 2015, texas instruments incorporated detailed description 129 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 6.13.1 peripheral file map table 6-43 lists the base address for each available peripheral. table 6-44 through table 6-78 list the registers and their offsets for each peripheral. table 6-43. peripherals offset address module name base address range special functions (see table 6-44 ) 0100h 000h-01fh pmm (see table 6-45 ) 0120h 000h-01fh fram control (see table 6-46 ) 0140h 000h-00fh crc16 (see table 6-47 ) 0150h 000h-007h ram controller (see table 6-48 ) 0158h 000h-001h watchdog (see table 6-49 ) 015ch 000h-001h cs (see table 6-50 ) 0160h 000h-00fh sys (see table 6-51 ) 0180h 000h-01fh shared reference (see table 6-52 ) 01b0h 000h-001h port p1/p2 (see table 6-53 ) 0200h 000h-01fh port p3/p4 (see table 6-54 ) 0220h 000h-01fh port p5/p6 (see table 6-55 ) 0240h 000h-01fh port p7/p8 (see table 6-56 ) 0260h 000h-01fh port p9/p10 (see table 6-57 ) 0280h 000h-01fh port pj (see table 6-58 ) 0320h 000h-01fh timer_a ta0 (see table 6-59 ) 0340h 000h-02fh timer_a ta1 (see table 6-60 ) 0380h 000h-02fh timer_b tb0 (see table 6-61 ) 03c0h 000h-02fh timer_a ta2 (see table 6-62 ) 0400h 000h-02fh capacitive touch io 0 (see table 6-63 ) 0430h 000h-00fh timer_a ta3 (see table 6-64 ) 0440h 000h-02fh capacitive touch io 1 (see table 6-65 ) 0470h 000h-00fh real-time clock (rtc_c) (see table 6-66 ) 04a0h 000h-01fh 32-bit hardware multiplier (see table 6-67 ) 04c0h 000h-02fh dma general control (see table 6-68 ) 0500h 000h-00fh dma channel 0 (see table 6-68 ) 0510h 000h-00fh dma channel 1 (see table 6-68 ) 0520h 000h-00fh dma channel 2 (see table 6-68 ) 0530h 000h-00fh mpu control (see table 6-69 ) 05a0h 000h-00fh eusci_a0 (see table 6-70 ) 05c0h 000h-01fh eusci_a1 (see table 6-71 ) 05e0h 000h-01fh eusci_b0 (see table 6-72 ) 0640h 000h-02fh eusci_b1 (see table 6-73 ) 0680h 000h-02fh adc12_b (see table 6-74 ) 0800h 000h-09fh comparator_e (see table 6-75 ) 08c0h 000h-00fh crc32 (see table 6-76 ) 0980h 000h-02fh lcd_c (see table 6-77 ) 0a00h 000h-05fh esi (see table 6-78 ) 0d00h 000h-09fh esi ram (128 bytes) 0e00h 00h-07fh 130 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 6-44. special function registers (base address: 0100h) register description register offset sfr interrupt enable sfrie1 00h sfr interrupt flag sfrifg1 02h sfr reset pin control sfrrpcr 04h table 6-45. pmm registers (base address: 0120h) register description register offset pmm control 0 pmmctl0 00h pmm interrupt flags pmmifg 0ah pm5 control 0 pm5ctl0 10h table 6-46. fram control registers (base address: 0140h) register description register offset fram control 0 frctl0 00h general control 0 gcctl0 04h general control 1 gcctl1 06h table 6-47. crc16 registers (base address: 0150h) register description register offset crc data input crc16di 00h crc data input reverse byte crcdirb 02h crc initialization and result crcinires 04h crc result reverse byte crcresr 06h table 6-48. ram controller registers (base address: 0158h) register description register offset ram controller control register 0 rcctl0 00h table 6-49. watchdog registers (base address: 015ch) register description register offset watchdog timer control wdtctl 00h table 6-50. cs registers (base address: 0160h) register description register offset cs control 0 csctl0 00h cs control 1 csctl1 02h cs control 2 csctl2 04h cs control 3 csctl3 06h cs control 4 csctl4 08h cs control 5 csctl5 0ah cs control 6 csctl6 0ch table 6-51. sys registers (base address: 0180h) register description register offset system control sysctl 00h jtag mailbox control sysjmbc 06h copyright ? 2014 ? 2015, texas instruments incorporated detailed description 131 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com table 6-51. sys registers (base address: 0180h) (continued) register description register offset jtag mailbox input 0 sysjmbi0 08h jtag mailbox input 1 sysjmbi1 0ah jtag mailbox output 0 sysjmbo0 0ch jtag mailbox output 1 sysjmbo1 0eh user nmi vector generator sysuniv 1ah system nmi vector generator syssniv 1ch reset vector generator sysrstiv 1eh table 6-52. shared reference registers (base address: 01b0h) register description register offset shared reference control refctl 00h table 6-53. port p1, p2 registers (base address: 0200h) register description register offset port p1 input p1in 00h port p1 output p1out 02h port p1 direction p1dir 04h port p1 pullup/pulldown enable p1ren 06h port p1 selection 0 p1sel0 0ah port p1 selection 1 p1sel1 0ch port p1 interrupt vector word p1iv 0eh port p1 complement selection p1selc 16h port p1 interrupt edge select p1ies 18h port p1 interrupt enable p1ie 1ah port p1 interrupt flag p1ifg 1ch port p2 input p2in 01h port p2 output p2out 03h port p2 direction p2dir 05h port p2 pullup/pulldown enable p2ren 07h port p2 selection 0 p2sel0 0bh port p2 selection 1 p2sel1 0dh port p2 complement selection p2selc 17h port p2 interrupt vector word p2iv 1eh port p2 interrupt edge select p2ies 19h port p2 interrupt enable p2ie 1bh port p2 interrupt flag p2ifg 1dh table 6-54. port p3, p4 registers (base address: 0220h) register description register offset port p3 input p3in 00h port p3 output p3out 02h port p3 direction p3dir 04h port p3 pullup/pulldown enable p3ren 06h port p3 selection 0 p3sel0 0ah port p3 selection 1 p3sel1 0ch port p3 interrupt vector word p3iv 0eh 132 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 6-54. port p3, p4 registers (base address: 0220h) (continued) register description register offset port p3 complement selection p3selc 16h port p3 interrupt edge select p3ies 18h port p3 interrupt enable p3ie 1ah port p3 interrupt flag p3ifg 1ch port p4 input p4in 01h port p4 output p4out 03h port p4 direction p4dir 05h port p4 pullup/pulldown enable p4ren 07h port p4 selection 0 p4sel0 0bh port p4 selection 1 p4sel1 0dh port p4 complement selection p4selc 17h port p4 interrupt vector word p4iv 1eh port p4 interrupt edge select p4ies 19h port p4 interrupt enable p4ie 1bh port p4 interrupt flag p4ifg 1dh table 6-55. port p5, p6 registers (base address: 0240h) register description register offset port p5 input p5in 00h port p5 output p5out 02h port p5 direction p5dir 04h port p5 pullup/pulldown enable p5ren 06h port p5 selection 0 p5sel0 0ah port p5 selection 1 p5sel1 0ch reserved 0eh port p5 complement selection p5selc 16h reserved 18h reserved 1ah reserved 1ch port p6 input p6in 01h port p6 output p6out 03h port p6 direction p6dir 05h port p6 pullup/pulldown enable p6ren 07h port p6 selection 0 p6sel0 0bh port p6 selection 1 p6sel1 0dh port p6 complement selection p6selc 17h reserved 1eh reserved 19h reserved 1bh reserved 1dh table 6-56. port p7, p8 registers (base address: 0260h) register description register offset port p7 input p7in 00h port p7 output p7out 02h port p7 direction p7dir 04h port p7 pullup/pulldown enable p7ren 06h copyright ? 2014 ? 2015, texas instruments incorporated detailed description 133 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com table 6-56. port p7, p8 registers (base address: 0260h) (continued) register description register offset port p7 selection 0 p7sel0 0ah port p7 selection 1 p7sel1 0ch reserved 0eh port p7 complement selection p7selc 16h reserved 18h reserved 1ah reserved 1ch port p8 input p8in 01h port p8 output p8out 03h port p8 direction p8dir 05h port p8 pullup/pulldown enable p8ren 07h port p8 selection 0 p8sel0 0bh port p8 selection 1 p8sel1 0dh port p8 complement selection p8selc 17h reserved 1eh reserved 19h reserved 1bh reserved 1dh table 6-57. port p9, p10 registers (base address: 0280h) register description register offset port p9 input p9in 00h port p9 output p9out 02h port p9 direction p9dir 04h port p9 pullup/pulldown enable p9ren 06h port p9 selection 0 p9sel0 0ah port p9 selection 1 p9sel1 0ch reserved 0eh port p9 complement selection p9selc 16h reserved 18h reserved 1ah reserved 1ch port p10 input p10in 01h port p10 output p10out 03h port p10 direction p10dir 05h port p10 pullup/pulldown enable p10ren 07h port p10 selection 0 p10sel0 0bh port p10 selection 1 p10sel1 0dh port p10 complement selection p10selc 17h reserved 1eh reserved 19h reserved 1bh reserved 1dh 134 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 6-58. port j registers (base address: 0320h) register description register offset port pj input pjin 00h port pj output pjout 02h port pj direction pjdir 04h port pj pullup/pulldown enable pjren 06h port pj selection 0 pjsel0 0ah port pj selection 1 pjsel1 0ch port pj complement selection pjselc 16h table 6-59. timer_a ta0 registers (base address: 0340h) register description register offset ta0 control ta0ctl 00h capture/compare control 0 ta0cctl0 02h capture/compare control 1 ta0cctl1 04h capture/compare control 2 ta0cctl2 06h capture/compare control 3 ta0cctl3 08h capture/compare control 4 ta0cctl4 0ah ta0 counter register ta0r 10h capture/compare register 0 ta0ccr0 12h capture/compare register 1 ta0ccr1 14h capture/compare register 2 ta0ccr2 16h capture/compare register 3 ta0ccr3 18h capture/compare register 4 ta0ccr4 1ah ta0 expansion register 0 ta0ex0 20h ta0 interrupt vector ta0iv 2eh table 6-60. timer_a ta1 registers (base address: 0380h) register description register offset ta1 control ta1ctl 00h capture/compare control 0 ta1cctl0 02h capture/compare control 1 ta1cctl1 04h capture/compare control 2 ta1cctl2 06h ta1 counter register ta1r 10h capture/compare register 0 ta1ccr0 12h capture/compare register 1 ta1ccr1 14h capture/compare register 2 ta1ccr2 16h ta1 expansion register 0 ta1ex0 20h ta1 interrupt vector ta1iv 2eh table 6-61. timer_b tb0 registers (base address: 03c0h) register description register offset tb0 control tb0ctl 00h capture/compare control 0 tb0cctl0 02h capture/compare control 1 tb0cctl1 04h capture/compare control 2 tb0cctl2 06h capture/compare control 3 tb0cctl3 08h capture/compare control 4 tb0cctl4 0ah copyright ? 2014 ? 2015, texas instruments incorporated detailed description 135 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com table 6-61. timer_b tb0 registers (base address: 03c0h) (continued) register description register offset capture/compare control 5 tb0cctl5 0ch capture/compare control 6 tb0cctl6 0eh tb0 register tb0r 10h capture/compare register 0 tb0ccr0 12h capture/compare register 1 tb0ccr1 14h capture/compare register 2 tb0ccr2 16h capture/compare register 3 tb0ccr3 18h capture/compare register 4 tb0ccr4 1ah capture/compare register 5 tb0ccr5 1ch capture/compare register 6 tb0ccr6 1eh tb0 expansion register 0 tb0ex0 20h tb0 interrupt vector tb0iv 2eh table 6-62. timer_a ta2 registers (base address: 0400h) register description register offset ta2 control ta2ctl 00h capture/compare control 0 ta2cctl0 02h capture/compare control 1 ta2cctl1 04h ta2 register ta2r 10h capture/compare register 0 ta2ccr0 12h capture/compare register 1 ta2ccr1 14h ta2 expansion register 0 ta2ex0 20h ta2 interrupt vector ta2iv 2eh table 6-63. capacitive touch io 0 registers (base address: 0430h) register description register offset capacitive touch io 0 control captio0ctl 0eh table 6-64. timer_a ta3 registers (base address: 0440h) register description register offset ta3 control ta3ctl 00h capture/compare control 0 ta3cctl0 02h capture/compare control 1 ta3cctl1 04h capture/compare control 2 ta3cctl2 06h capture/compare control 3 ta3cctl3 08h capture/compare control 4 ta3cctl4 0ah ta3 register ta3r 10h capture/compare register 0 ta3ccr0 12h capture/compare register 1 ta3ccr1 14h capture/compare register 2 ta3ccr2 16h capture/compare register 3 ta3ccr3 18h capture/compare register 4 ta3ccr4 1ah ta3 expansion register 0 ta3ex0 20h ta3 interrupt vector ta3iv 2eh 136 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 6-65. capacitive touch io 1 registers (base address: 0470h) register description register offset capacitive touch io 1 control captio1ctl 0eh table 6-66. rtc_c registers (base address: 04a0h) register description register offset rtc control 0 rtcctl0 00h rtc password rtcpwd 01h rtc control 1 rtcctl1 02h rtc control 3 rtcctl3 03h rtc offset calibration rtcocal 04h rtc temperature compensation rtctcmp 06h rtc prescaler 0 control rtcps0ctl 08h rtc prescaler 1 control rtcps1ctl 0ah rtc prescaler 0 rtcps0 0ch rtc prescaler 1 rtcps1 0dh rtc interrupt vector word rtciv 0eh rtc seconds/counter register 1 rtcsec/rtcnt1 10h rtc minutes/counter register 2 rtcmin/rtcnt2 11h rtc hours/counter register 3 rtchour/rtcnt3 12h rtc day of week/counter register 4 rtcdow/rtcnt4 13h rtc days rtcday 14h rtc month rtcmon 15h rtc year rtcyear 16h rtc alarm minutes rtcamin 18h rtc alarm hours rtcahour 19h rtc alarm day of week rtcadow 1ah rtc alarm days rtcaday 1bh binary-to-bcd conversion register bin2bcd 1ch bcd-to-binary conversion register bcd2bin 1eh table 6-67. 32-bit hardware multiplier registers (base address: 04c0h) register description register offset 16-bit operand 1 ? multiply mpy 00h 16-bit operand 1 ? signed multiply mpys 02h 16-bit operand 1 ? multiply accumulate mac 04h 16-bit operand 1 ? signed multiply accumulate macs 06h 16-bit operand 2 op2 08h 16 16 result low word reslo 0ah 16 16 result high word reshi 0ch 16 16 sum extension register sumext 0eh 32-bit operand 1 ? multiply low word mpy32l 10h 32-bit operand 1 ? multiply high word mpy32h 12h 32-bit operand 1 ? signed multiply low word mpys32l 14h 32-bit operand 1 ? signed multiply high word mpys32h 16h 32-bit operand 1 ? multiply accumulate low word mac32l 18h 32-bit operand 1 ? multiply accumulate high word mac32h 1ah 32-bit operand 1 ? signed multiply accumulate low word macs32l 1ch 32-bit operand 1 ? signed multiply accumulate high word macs32h 1eh copyright ? 2014 ? 2015, texas instruments incorporated detailed description 137 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com table 6-67. 32-bit hardware multiplier registers (base address: 04c0h) (continued) register description register offset 32-bit operand 2 ? low word op2l 20h 32-bit operand 2 ? high word op2h 22h 32 32 result 0 ? least significant word res0 24h 32 32 result 1 res1 26h 32 32 result 2 res2 28h 32 32 result 3 ? most significant word res3 2ah mpy32 control register 0 mpy32ctl0 2ch table 6-68. dma registers (base address dma general control: 0500h, dma channel 0: 0510h, dma channel 1: 0520h, dma channel 2: 0530h) register description register offset dma channel 0 control dma0ctl 00h dma channel 0 source address low dma0sal 02h dma channel 0 source address high dma0sah 04h dma channel 0 destination address low dma0dal 06h dma channel 0 destination address high dma0dah 08h dma channel 0 transfer size dma0sz 0ah dma channel 1 control dma1ctl 00h dma channel 1 source address low dma1sal 02h dma channel 1 source address high dma1sah 04h dma channel 1 destination address low dma1dal 06h dma channel 1 destination address high dma1dah 08h dma channel 1 transfer size dma1sz 0ah dma channel 2 control dma2ctl 00h dma channel 2 source address low dma2sal 02h dma channel 2 source address high dma2sah 04h dma channel 2 destination address low dma2dal 06h dma channel 2 destination address high dma2dah 08h dma channel 2 transfer size dma2sz 0ah dma module control 0 dmactl0 00h dma module control 1 dmactl1 02h dma module control 2 dmactl2 04h dma module control 3 dmactl3 06h dma module control 4 dmactl4 08h dma interrupt vector dmaiv 0eh table 6-69. mpu control registers (base address: 05a0h) register description register offset mpu control 0 mpuctl0 00h mpu control 1 mpuctl1 02h mpu segmentation border 2 mpusegb2 04h mpu segmentation border 1 mpusegb1 06h mpu access management mpusam 08h mpu ip control 0 mpuipc0 0ah mpu ip encapsulation segment border 2 mpuipsegb2 0ch mpu ip encapsulation segment border 1 mpuipsegb1 0eh 138 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 6-70. eusci_a0 registers (base address: 05c0h) register description register offset eusci_a control word 0 uca0ctlw0 00h eusci _a control word 1 uca0ctlw1 02h eusci_a baud rate 0 uca0br0 06h eusci_a baud rate 1 uca0br1 07h eusci_a modulation control uca0mctlw 08h eusci_a status word uca0statw 0ah eusci_a receive buffer uca0rxbuf 0ch eusci_a transmit buffer uca0txbuf 0eh eusci_a lin control uca0abctl 10h eusci_a irda transmit control uca0irtctl 12h eusci_a irda receive control uca0irrctl 13h eusci_a interrupt enable uca0ie 1ah eusci_a interrupt flags uca0ifg 1ch eusci_a interrupt vector word uca0iv 1eh table 6-71. eusci_a1 registers (base address:05e0h) register description register offset eusci_a control word 0 uca1ctlw0 00h eusci _a control word 1 uca1ctlw1 02h eusci_a baud rate 0 uca1br0 06h eusci_a baud rate 1 uca1br1 07h eusci_a modulation control uca1mctlw 08h eusci_a status word uca1statw 0ah eusci_a receive buffer uca1rxbuf 0ch eusci_a transmit buffer uca1txbuf 0eh eusci_a lin control uca1abctl 10h eusci_a irda transmit control uca1irtctl 12h eusci_a irda receive control uca1irrctl 13h eusci_a interrupt enable uca1ie 1ah eusci_a interrupt flags uca1ifg 1ch eusci_a interrupt vector word uca1iv 1eh table 6-72. eusci_b0 registers (base address: 0640h) register description register offset eusci_b control word 0 ucb0ctlw0 00h eusci_b control word 1 ucb0ctlw1 02h eusci_b bit rate 0 ucb0br0 06h eusci_b bit rate 1 ucb0br1 07h eusci_b status word ucb0statw 08h eusci_b byte counter threshold ucb0tbcnt 0ah eusci_b receive buffer ucb0rxbuf 0ch eusci_b transmit buffer ucb0txbuf 0eh eusci_b i2c own address 0 ucb0i2coa0 14h eusci_b i2c own address 1 ucb0i2coa1 16h eusci_b i2c own address 2 ucb0i2coa2 18h eusci_b i2c own address 3 ucb0i2coa3 1ah eusci_b received address ucb0addrx 1ch copyright ? 2014 ? 2015, texas instruments incorporated detailed description 139 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com table 6-72. eusci_b0 registers (base address: 0640h) (continued) register description register offset eusci_b address mask ucb0addmask 1eh eusci_b i2c slave address ucb0i2csa 20h eusci_b interrupt enable ucb0ie 2ah eusci_b interrupt flags ucb0ifg 2ch eusci_b interrupt vector word ucb0iv 2eh table 6-73. eusci_b1 registers (base address: 0680h) register description register offset eusci_b control word 0 ucb1ctlw0 00h eusci_b control word 1 ucb1ctlw1 02h eusci_b bit rate 0 ucb1br0 06h eusci_b bit rate 1 ucb1br1 07h eusci_b status word ucb1statw 08h eusci_b byte counter threshold ucb1tbcnt 0ah eusci_b receive buffer ucb1rxbuf 0ch eusci_b transmit buffer ucb1txbuf 0eh eusci_b i2c own address 0 ucb1i2coa0 14h eusci_b i2c own address 1 ucb1i2coa1 16h eusci_b i2c own address 2 ucb1i2coa2 18h eusci_b i2c own address 3 ucb1i2coa3 1ah eusci_b received address ucb1addrx 1ch eusci_b address mask ucb1addmask 1eh eusci_b i2c slave address ucb1i2csa 20h eusci_b interrupt enable ucb1ie 2ah eusci_b interrupt flags ucb1ifg 2ch eusci_b interrupt vector word ucb1iv 2eh table 6-74. adc12_b registers (base address: 0800h) register description register offset adc12_b control 0 adc12ctl0 00h adc12_b control 1 adc12ctl1 02h adc12_b control 2 adc12ctl2 04h adc12_b control 3 adc12ctl3 06h adc12_b window comparator low threshold register adc12lo 08h adc12_b window comparator high threshold register adc12hi 0ah adc12_b interrupt flag register 0 adc12ifgr0 0ch adc12_b interrupt flag register 1 adc12ifgr1 0eh adc12_b interrupt flag register 2 adc12ifgr2 10h adc12_b interrupt enable register 0 adc12ier0 12h adc12_b interrupt enable register 1 adc12ier1 14h adc12_b interrupt enable register 2 adc12ier2 16h adc12_b interrupt vector adc12iv 18h adc12_b memory control 0 adc12mctl0 20h adc12_b memory control 1 adc12mctl1 22h adc12_b memory control 2 adc12mctl2 24h adc12_b memory control 3 adc12mctl3 26h adc12_b memory control 4 adc12mctl4 28h 140 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 6-74. adc12_b registers (base address: 0800h) (continued) register description register offset adc12_b memory control 5 adc12mctl5 2ah adc12_b memory control 6 adc12mctl6 2ch adc12_b memory control 7 adc12mctl7 2eh adc12_b memory control 8 adc12mctl8 30h adc12_b memory control 9 adc12mctl9 32h adc12_b memory control 10 adc12mctl10 34h adc12_b memory control 11 adc12mctl11 36h adc12_b memory control 12 adc12mctl12 38h adc12_b memory control 13 adc12mctl13 3ah adc12_b memory control 14 adc12mctl14 3ch adc12_b memory control 15 adc12mctl15 3eh adc12_b memory control 16 adc12mctl16 40h adc12_b memory control 17 adc12mctl17 42h adc12_b memory control 18 adc12mctl18 44h adc12_b memory control 19 adc12mctl19 46h adc12_b memory control 20 adc12mctl20 48h adc12_b memory control 21 adc12mctl21 4ah adc12_b memory control 22 adc12mctl22 4ch adc12_b memory control 23 adc12mctl23 4eh adc12_b memory control 24 adc12mctl24 50h adc12_b memory control 25 adc12mctl25 52h adc12_b memory control 26 adc12mctl26 54h adc12_b memory control 27 adc12mctl27 56h adc12_b memory control 28 adc12mctl28 58h adc12_b memory control 29 adc12mctl29 5ah adc12_b memory control 30 adc12mctl30 5ch adc12_b memory control 31 adc12mctl31 5eh adc12_b memory 0 adc12mem0 60h adc12_b memory 1 adc12mem1 62h adc12_b memory 2 adc12mem2 64h adc12_b memory 3 adc12mem3 66h adc12_b memory 4 adc12mem4 68h adc12_b memory 5 adc12mem5 6ah adc12_b memory 6 adc12mem6 6ch adc12_b memory 7 adc12mem7 6eh adc12_b memory 8 adc12mem8 70h adc12_b memory 9 adc12mem9 72h adc12_b memory 10 adc12mem10 74h adc12_b memory 11 adc12mem11 76h adc12_b memory 12 adc12mem12 78h adc12_b memory 13 adc12mem13 7ah adc12_b memory 14 adc12mem14 7ch adc12_b memory 15 adc12mem15 7eh adc12_b memory 16 adc12mem16 80h adc12_b memory 17 adc12mem17 82h adc12_b memory 18 adc12mem18 84h adc12_b memory 19 adc12mem19 86h copyright ? 2014 ? 2015, texas instruments incorporated detailed description 141 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com table 6-74. adc12_b registers (base address: 0800h) (continued) register description register offset adc12_b memory 20 adc12mem20 88h adc12_b memory 21 adc12mem21 8ah adc12_b memory 22 adc12mem22 8ch adc12_b memory 23 adc12mem23 8eh adc12_b memory 24 adc12mem24 90h adc12_b memory 25 adc12mem25 92h adc12_b memory 26 adc12mem26 94h adc12_b memory 27 adc12mem27 96h adc12_b memory 28 adc12mem28 98h adc12_b memory 29 adc12mem29 9ah adc12_b memory 30 adc12mem30 9ch adc12_b memory 31 adc12mem31 9eh table 6-75. comparator_e registers (base address: 08c0h) register description register offset comparator control register 0 cectl0 00h comparator control register 1 cectl1 02h comparator control register 2 cectl2 04h comparator control register 3 cectl3 06h comparator interrupt register ceint 0ch comparator interrupt vector word ceiv 0eh table 6-76. crc32 registers (base address: 0980h) register description register offset crc32 data input crc32diw0 00h reserved 02h reserved 04h crc32 data input reverse crc32dirbw0 06h crc32 initialization and result word 0 crc32iniresw0 08h crc32 initialization and result word 1 crc32iniresw1 0ah crc32 result reverse word 1 crc32resrw1 0ch crc32 result reverse word 0 crc32resrw1 0eh crc16 data input crc16diw0 10h reserved 12h reserved 14h crc16 data input reverse crc16dirbw0 16h crc16 initialization and result word 0 crc16iniresw0 18h reserved 1ah reserved 1ch crc16 result reverse word 0 crc16resrw1 1eh reserved 20h reserved 22h reserved 24h reserved 26h reserved 28h reserved 2ah reserved 2ch 142 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 6-76. crc32 registers (base address: 0980h) (continued) register description register offset reserved 2eh table 6-77. lcd_c registers (base address: 0a00h) register description register offset lcd_c control register 0 lcdcctl0 000h lcd_c control register 1 lcdcctl1 002h lcd_c blinking control register lcdcblkctl 004h lcd_c memory control register lcdcmemctl 006h lcd_c voltage control register lcdcvctl 008h lcd_c port control 0 lcdcpctl0 00ah lcd_c port control 1 lcdcpctl1 00ch lcd_c port control 2 lcdcpctl2 00eh lcd_c charge pump control register lcdccpctl 012h lcd_c interrupt vector lcdciv 01eh static and 2 to 4 mux modes lcd_c memory 1 lcdm1 020h lcd_c memory 2 lcdm2 021h lcd_c memory 3 lcdm3 022h lcd_c memory 4 lcdm4 023h lcd_c memory 5 lcdm5 024h lcd_c memory 6 lcdm6 025h lcd_c memory 7 lcdm7 026h lcd_c memory 8 lcdm8 027h lcd_c memory 9 lcdm9 028h lcd_c memory 10 lcdm10 029h lcd_c memory 11 lcdm11 02ah lcd_c memory 12 lcdm12 02bh lcd_c memory 13 lcdm13 02ch lcd_c memory 14 lcdm14 02dh lcd_c memory 15 lcdm15 02eh lcd_c memory 16 lcdm16 02fh lcd_c memory 17 lcdm17 030h lcd_c memory 18 lcdm18 031h lcd_c memory 19 lcdm19 032h lcd_c memory 20 lcdm20 033h lcd_c memory 21 lcdm21 034h lcd_c memory 22 lcdm22 035h reserved 036h reserved 037h lcd_c blinking memory 1 lcdbm1 040h lcd_c blinking memory 2 lcdbm2 041h lcd_c blinking memory 3 lcdbm3 042h lcd_c blinking memory 4 lcdbm4 043h lcd_c blinking memory 5 lcdbm5 044h lcd_c blinking memory 6 lcdbm6 045h lcd_c blinking memory 7 lcdbm7 046h lcd_c blinking memory 8 lcdbm8 047h copyright ? 2014 ? 2015, texas instruments incorporated detailed description 143 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com table 6-77. lcd_c registers (base address: 0a00h) (continued) register description register offset lcd_c blinking memory 9 lcdbm9 048h lcd_c blinking memory 10 lcdbm10 049h lcd_c blinking memory 11 lcdbm11 04ah lcd_c blinking memory 12 lcdbm12 04bh lcd_c blinking memory 13 lcdbm13 04ch lcd_c blinking memory 14 lcdbm14 04dh lcd_c blinking memory 15 lcdbm15 04eh lcd_c blinking memory 16 lcdbm16 04fh lcd_c blinking memory 17 lcdbm17 050h lcd_c blinking memory 18 lcdbm18 051h lcd_c blinking memory 19 lcdbm19 052h lcd_c blinking memory 20 lcdbm20 053h lcd_c blinking memory 21 lcdbm21 054h lcd_c blinking memory 22 lcdbm22 055h reserved 056h reserved 057h 5 to 8 mux modes lcd_c memory 1 lcdm1 020h lcd_c memory 2 lcdm2 021h lcd_c memory 3 lcdm3 022h lcd_c memory 4 lcdm4 023h lcd_c memory 5 lcdm5 024h lcd_c memory 6 lcdm6 025h lcd_c memory 7 lcdm7 026h lcd_c memory 8 lcdm8 027h lcd_c memory 9 lcdm9 028h lcd_c memory 10 lcdm10 029h lcd_c memory 11 lcdm11 02ah lcd_c memory 12 lcdm12 02bh lcd_c memory 13 lcdm13 02ch lcd_c memory 14 lcdm14 02dh lcd_c memory 15 lcdm15 02eh lcd_c memory 16 lcdm16 02fh lcd_c memory 17 lcdm17 030h lcd_c memory 18 lcdm18 031h lcd_c memory 19 lcdm19 032h lcd_c memory 20 lcdm20 033h lcd_c memory 21 lcdm21 034h lcd_c memory 22 lcdm22 035h lcd_c memory 23 lcdm23 036h lcd_c memory 24 lcdm24 037h lcd_c memory 25 lcdm25 038h lcd_c memory 26 lcdm26 039h lcd_c memory 27 lcdm27 03ah lcd_c memory 28 lcdm28 03bh lcd_c memory 29 lcdm29 03ch lcd_c memory 30 lcdm30 03dh 144 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 6-77. lcd_c registers (base address: 0a00h) (continued) register description register offset lcd_c memory 31 lcdm31 03eh lcd_c memory 32 lcdm32 03fh lcd_c memory 33 lcdm33 040h lcd_c memory 34 lcdm34 041h lcd_c memory 35 lcdm35 042h lcd_c memory 36 lcdm36 043h lcd_c memory 37 lcdm37 044h lcd_c memory 38 lcdm38 045h lcd_c memory 39 lcdm39 046h lcd_c memory 40 lcdm40 047h lcd_c memory 41 lcdm41 048h lcd_c memory 42 lcdm42 049h lcd_c memory 43 lcdm43 04ah table 6-78. extended scan interface (esi) registers (base address: 0d00h) register description register offset esi debug register 1 esidebug1 000h esi debug register 2 esidebug2 002h esi debug register 3 esidebug3 004h esi debug register 4 esidebug4 006h esi debug register 5 esidebug5 008h reserved 00ah reserved 00ch reserved 00eh esi psm counter 0 esicnt0 010h esi psm counter 1 esicnt1 012h esi psm counter 2 esicnt2 014h esi oscillator counter register esicnt3 016h reserved 018h esi interrupt vector esiiv 01ah esi interrupt register 1 esiint1 01ch esi interrupt register 2 esiint2 01eh esi afe control register esiafe 020h esi ppu control register esippu 022h esi tsm control register esitsm 024h esi psm control register esipsm 026h esi oscillator control register esiosc 028h esi control register esictl 02ah esi psm counter threshold register 1 esithr1 02ch esi psm counter threshold register 2 esithr2 02eh esi a/d conversion memory 1 esiadmem1 030h esi a/d conversion memory 2 esiadmem2 032h esi a/d conversion memory 3 esiadmem3 034h esi a/d conversion memory 4 esiadmem4 036h reserved 038h reserved 03ah reserved 03ch copyright ? 2014 ? 2015, texas instruments incorporated detailed description 145 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com table 6-78. extended scan interface (esi) registers (base address: 0d00h) (continued) register description register offset reserved 03eh esi dac1 register 0 esidac1r0 040h esi dac1 register 1 esidac1r1 042h esi dac1 register 2 esidac1r2 044h esi dac1 register 3 esidac1r3 046h esi dac1 register 4 esidac1r4 048h esi dac1 register 5 esidac1r5 04ah esi dac1 register 6 esidac1r6 04ch esi dac1 register 7 esidac1r7 04eh esi dac2 register 0 esidac2r0 050h esi dac2 register 1 esidac2r1 052h esi dac2 register 2 esidac2r2 054h esi dac2 register 3 esidac2r3 056h esi dac2 register 4 esidac2r4 058h esi dac2 register 5 esidac2r5 05ah esi dac2 register 6 esidac2r6 05ch esi dac2 register 7 esidac2r7 05eh esi tsm 0 esitsm0 060h esi tsm 1 esitsm1 062h esi tsm 2 esitsm2 064h esi tsm 3 esitsm3 066h esi tsm 4 esitsm4 068h esi tsm 5 esitsm5 06ah esi tsm 6 esitsm6 06ch esi tsm 7 esitsm7 06eh esi tsm 8 esitsm8 070h esi tsm 9 esitsm9 072h esi tsm 10 esitsm10 074h esi tsm 11 esitsm11 076h esi tsm 12 esitsm12 078h esi tsm 13 esitsm13 07ah esi tsm 14 esitsm14 07ch esi tsm 15 esitsm15 07eh esi tsm 16 esitsm16 080h esi tsm 17 esitsm17 082h esi tsm 18 esitsm18 084h esi tsm 19 esitsm19 086h esi tsm 20 esitsm20 088h esi tsm 21 esitsm21 08ah esi tsm 22 esitsm22 08ch esi tsm 23 esitsm23 08eh esi tsm 24 esitsm24 090h esi tsm 25 esitsm25 092h esi tsm 26 esitsm26 094h esi tsm 27 esitsm27 096h esi tsm 28 esitsm28 098h esi tsm 29 esitsm29 09ah 146 detailed description copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 table 6-78. extended scan interface (esi) registers (base address: 0d00h) (continued) register description register offset esi tsm 30 esitsm30 09ch esi tsm 31 esitsm31 09eh 6.14 identification 6.14.1 revision identification the device revision information is shown as part of the top-side marking on the device package. the device-specific errata sheet describes these markings. for links to all of the errata sheets for the devices in this data sheet, see section 8.2 . the hardware revision is also stored in the device descriptor structure in the info block section. for details on this value, see the "hardware revision" entries in section 6.12 . 6.14.2 device identification the device type can be identified from the top-side marking on the device package. the device-specific errata sheet describes these markings. for links to all of the errata sheets for the devices in this data sheet, see section 8.2 . a device identification value is also stored in the device descriptor structure in the info block section. for details on this value, see the "device id" entries in section 6.12 . 6.14.3 jtag identification programming through the jtag interface, including reading and identifying the jtag id, is described in detail in the msp430 programming via the jtag interface user's guide ( slau320 ). copyright ? 2014 ? 2015, texas instruments incorporated detailed description 147 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 7 applications, implementation, and layout note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 7.1 device connection and layout fundamentals this section discusses the recommended guidelines when designing with the msp430. these guidelines are to make sure that the device has proper connections for powering, programming, debugging, and optimum analog performance. 7.1.1 power supply decoupling and bulk capacitors ti recommends connecting a combination of a 1- f plus a 100-nf low-esr ceramic decoupling capacitor to each avcc, dvcc, and esidvcc pin. higher-value capacitors may be used but can impact supply rail ramp-up time. decoupling capacitors must be placed as close as possible to the pins that they decouple (within a few millimeters). additionally, separated grounds with a single-point connection are recommend for better noise isolation from digital to analog circuits on the board and are especially recommended to achieve high analog accuracy. figure 7-1. power supply decoupling 7.1.2 external oscillator depending on the device variant (see section 3 ), the device can support a low-frequency crystal (32 khz) on the lfxt pins, a high-frequency crystal on the hfxt pins, or both. external bypass capacitors for the crystal oscillator pins are required. it is also possible to apply digital clock signals to the lfxin and hfxin input pins that meet the specifications of the respective oscillator if the appropriate lfxtbypass or hfxtbypass mode is selected. in this case, the associated lfxout and hfxout pins can be used for other purposes. if they are left unused, they must be terminated according to section 4.6 . figure 7-2 shows a typical connection diagram. 148 applications, implementation, and layout copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 digital power supply decoupling 100 nf 1 f analog power supply decoupling dvcc, esidvcc dvss, esidvss avcc avss + + 100 nf 1 f
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 figure 7-2. typical crystal connection see the application report msp430 32-khz crystal oscillators ( slaa322 ) for more information on selecting, testing, and designing a crystal oscillator with the msp430 devices. 7.1.3 jtag with the proper connections, the debugger and a hardware jtag interface (such as the msp-fet or msp-fet430uif) can be used to program and debug code on the target board. in addition, the connections also support the msp-gang production programmers, thus providing an easy way to program prototype boards, if desired. figure 7-3 shows the connections between the 14-pin jtag connector and the target device required to support in-system programming and debugging for 4-wire jtag communication. figure 7-4 shows the connections for 2-wire jtag mode (spy-bi-wire). the connections for the msp-fet and msp-fet430uif interface modules and the msp-gang are identical. both can supply vcc to the target board (through pin 2). in addition, the msp-fet and msp- fet430uif interface modules and msp-gang have a vcc sense feature that, if used, requires an alternate connection (pin 4 instead of pin 2). the vcc-sense feature senses the local vcc present on the target board (that is, a battery or other local power supply) and adjusts the output signals accordingly. figure 7-3 and figure 7-4 show a jumper block that supports both scenarios of supplying vcc to the target board. if this flexibility is not required, the desired vcc connections may be hard-wired to eliminate the jumper block. pins 2 and 4 must not be connected at the same time. for additional design information regarding the jtag interface, see the msp430 hardware tools user's guide ( slau278 ). copyright ? 2014 ? 2015, texas instruments incorporated applications, implementation, and layout 149 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 c l1 c l2 lfxin or hfxin lfxout or hfxout
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com a. if a local target power supply is used, make connection j1. if power from the debug or programming adapter is used, make connection j2. b. the upper limit for c1 is 2.2 nf when using current ti tools. figure 7-3. signal connections for 4-wire jtag communication 150 applications, implementation, and layout copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 1 35 7 9 11 13 24 6 8 10 12 14 tdo/tditdi tms tck gnd test jtag vcc tool vcc target j1 (see note a) j2 (see note a) v cc r1 47 k w av /dvcc cc rst/nmi/sbwtdio tdo/tditdi tms tck test/sbwtck av /dv ss ss msp430frxxx c1 2.2 nf (see note b) rst important to connect
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 a. make connection j1 if a local target power supply is used, or make connection j2 if the target is powered from the debug or programming adapter. b. the device rst/nmi/sbwtdio pin is used in 2-wire mode for bidirectional communication with the device during jtag access, and any capacitance that is attached to this signal may affect the ability to establish a connection with the device. the upper limit for c1 is 2.2 nf when using current ti tools. figure 7-4. signal connections for 2-wire jtag communication (spy-bi-wire) 7.1.4 reset the reset pin can be configured as a reset function (default) or as an nmi function in the special function register (sfr), sfrrpcr. in reset mode, the rst/nmi pin is active low, and a pulse applied to this pin that meets the reset timing specifications generates a bor-type device reset. setting sysnmi causes the rst/nmi pin to be configured as an external nmi source. the external nmi is edge sensitive, and its edge is selectable by sysnmiies. setting the nmiie enables the interrupt of the external nmi. when an external nmi event occurs, the nmiifg is set. the rst/nmi pin can have either a pullup or pulldown that is enabled or not. sysrstup selects either pullup or pulldown, and sysrstre causes the pullup (default) or pulldown to be enabled (default) or not. if the rst/nmi pin is unused, it is required either to select and enable the internal pullup or to connect an external 47-k pullup resistor to the rst/nmi pin with a 2.2-nf pulldown capacitor. the pulldown capacitor should not exceed 2.2 nf when using devices with spy-bi-wire interface in spy-bi-wire mode or in 4-wire jtag mode with ti tools like fet interfaces or gang programmers. see the msp430fr58xx, msp430fr59xx, msp430fr68xx, and msp430fr69xx family user's guide ( slau367 ) for more information on the referenced control registers and bits. 7.1.5 unused pins for details on the connection of unused pins, see section 4.6 . copyright ? 2014 ? 2015, texas instruments incorporated applications, implementation, and layout 151 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 13 5 7 9 11 13 24 6 8 10 12 14 test/sbwtck msp430frxxx rst/nmi/sbwtdio tdo/tdi tck gnd jtag r1 47 k see note b vcc tool vcc target c1 2.2 nf see note b j1 (see note a) j2 (see note a) important to connect av /dvcc cc av /dv ss ss v cc
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 7.1.6 general layout recommendations ? proper grounding and short traces for external crystal to reduce parasitic capacitance. see the application report msp430 32-khz crystal oscillators ( slaa322 ) for recommended layout guidelines. ? proper bypass capacitors on dvcc, avcc, and reference pins if used. ? avoid routing any high-frequency signal close to an analog signal line. for example, keep digital switching signals such as pwm or jtag signals away from the oscillator circuit. ? refer to the circuit board layout techniques design guide ( sloa089 ) for a detailed discussion of pcb layout considerations. this document is written primarily about op amps, but the guidelines are generally applicable for all mixed-signal applications. ? proper esd level protection should be considered to protect the device from unintended high-voltage electrostatic discharge. see the application report msp430 system-level esd considerations ( slaa530 ) for guidelines. 7.1.7 do ' s and don ' ts ti recommendeds powering the avcc, dvcc, and esidvcc pins from the same source. at a minimum, during power up, power down, and device operation, the voltage difference between avcc and dvcc must not exceed the limits specified in the absolute maximum ratings section. exceeding the specified limits may cause malfunction of the device including erroneous writes to ram and fram. 7.2 peripheral- and interface-specific design information 7.2.1 adc12_b peripheral 7.2.1.1 partial schematic figure 7-5. adc12_b grounding and noise considerations 7.2.1.2 design requirements as with any high-resolution adc, appropriate printed-circuit-board layout and grounding techniques should be followed to eliminate ground loops, unwanted parasitic effects, and noise. ground loops are formed when return current from the adc flows through paths that are common with other analog or digital circuitry. if care is not taken, this current can generate small unwanted offset voltages that can add to or subtract from the reference or input voltages of the adc. the general guidelines in section 7.1.1 combined with the connections shown in section 7.2.1.1 prevent this. in addition to grounding, ripple and noise spikes on the power-supply lines that are caused by digital switching or switching power supplies can corrupt the conversion result. a noise-free design using separate analog and digital ground planes with a single-point connection is recommend to achieve high accuracy. 152 applications, implementation, and layout copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 using an external positive reference using an external negative reference veref- vref+/veref+ + + 4.7 f 10 f 4.7 f 10 f avss
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 figure 7-5 shows the recommended decoupling circuit when an external voltage reference is used. the internal reference module has a maximum drive current as specified in the reference module's i o(vref+) specification. the reference voltage must be a stable voltage for accurate measurements. the capacitor values that are selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage enters the device. in this case, the 10- f capacitor is used to buffer the reference pin and filter any low- frequency ripple. a bypass capacitor of 4.7 f is used to filter out any high frequency noise. 7.2.1.3 detailed design procedure for additional design information, see the application report designing with the msp430fr58xx, fr59xx, fr68xx, and fr69xx adc ( slaa624 ). 7.2.1.4 layout guidelines component that are shown in the partial schematic (see figure 7-5 ) should be placed as close as possible to the respective device pins. avoid long traces, because they add additional parasitic capacitance, inductance, and resistance on the signal. avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency pwm), because the high-frequency switching can be coupled into the analog signal. if differential mode is used for the adc12_b, the analog differential input signals must be routed closely together to minimize the effect of noise on the resulting signal. copyright ? 2014 ? 2015, texas instruments incorporated applications, implementation, and layout 153 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 7.2.2 lcd_c peripheral 7.2.2.1 partial schematic required lcd connections greatly vary by the type of display that is used (static or multiplexed), whether external or internal biasing is used, and also whether the on-chip charge pump is employed. for any display used, there is flexibility as to how the segment (sx) and common (comx) signals are connected to the mcu which (assuming that the correct choices are made) can be advantageous for the pcb layout and for the design of the application software. because lcd connections are application specific, it is difficult to provide a single one-fits-all schematic. however, for an example of connecting a 4-mux lcd with 40 segment lines that has a total of 4 40 = 160 individually addressable lcd segments to an msp430fr6989, see the gas or water meter with 2 lc sensors reference design ( tidm-lc-watermtr ). 7.2.2.2 design requirements due to the flexibility of the lcd_c peripheral module to accommodate various segment-based lcds, selecting the right display for the application in combination with determining specific design requirements is often an iterative process. there can be well-defined requirements in terms of how many individually addressable lcd segments need to be controlled, what the requirements for lcd contrast are, which device pins are available for lcd use and which are required by other application functions, and what the power budget is, to name just a few. ti strongly recommends reviewing the lcd_c peripheral module chapter in the msp430fr58xx, msp430fr59xx, msp430fr68xx, and msp430fr69xx family user's guide ( slau367 ) during the initial design requirements and decision process. the following table provides a brief overview over different choices that can be made and their impact. option or feature impact or use case ? enable displays with more segments ? use fewer device pins multiplexed lcd ? lcd contrast decreases as mux level increases ? power consumption increases with mux level ? requires multiple intermediate bias voltages ? limited number of segments that can be addressed ? use a relatively large number of device pins static lcd ? use the least amount of power ? use only v cc and gnd to drive lcd signals ? simpler solution ? no external circuitry internal bias generation ? independent of v lcd source ? somewhat higher power consumption ? requires external resistor ladder divider ? resistor size depends on display external bias generation ? ability to adjust drive strength to optimize tradeoff between power consumption and good drive of large segments (high capacitive load) ? external resistor ladder divider can be stabilized through capacitors to reduce ripple ? helps ensure a constant level of contrast despite decaying supply voltage conditions (battery-powered applications) internal charge pump ? programmable voltage levels allow software-driven contrast control ? requires an external capacitor on the lcdcap pin ? higher current consumption than simply using v cc for the lcd driver 154 applications, implementation, and layout copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 7.2.2.3 detailed design procedure a major component in designing the lcd solution is determining the exact connections between the lcd_c peripheral module and the display itself. two basic design processes can be employed for this step, although in reality often a balanced co-design approach is recommended: ? pcb layout-driven design ? software-driven design in the pcb layout-driven design process, the segment sx and common comx signals are connected to respective msp430 device pins so that the routing of the pcb can be optimized to minimize signal crossings and to keep signals on one side of the pcb only, typically the top layer. for example, using a multiplexed lcd, it is possible to arbitrarily connect the sx and comx signals between the lcd and the msp430 device as long as segment lines are swapped with segment lines and common lines are swapped with common lines. it is also possible to not contiguously connect all segment lines but rather skip lcd_c module segment connections to optimize layout or to allow access to other functions that may be multiplexed on a particular device port pin. employing a purely layout-driven design approach, however, can result in the lcd_c module control bits that are responsible for turning on and off segments to appear scattered throughout the memory map of the lcd controller (lcdmx registers). this approach potentially places a rather large burden on the software design that may also result in increased energy consumption due to the computational overhead required to work with the lcd. the other extreme is a purely software-driven approach that starts with the idea that control bits for lcd segments that are frequently turned on and off together should be co-located in memory in the same lcdmx register or in adjacent registers. for example, in case of a 4-mux display that contains several 7- segment digits, from a software perspective it can be very desirable to control all 7 segments of each digit though a single byte-wide access to an lcdmx register. and consecutive segments are mapped to consecutive lcdmx registers. this allows use of simple look-up tables or software loops to output numbers on an lcd, reducing computational overhead and optimizing the energy consumption of an application. establishing of the most convenient memory layout needs to be performed in conjunction with the specific lcd that is being used to understand its design constraints in terms of which segment and which common signals are connected to, for example, a digit. for design information regarding the lcd controller input voltage selection including internal and external options, contrast control, and bias generation, refer to the lcd_c controller chapter in the msp430fr58xx, msp430fr59xx, msp430fr68xx, and msp430fr69xx family user's guide ( slau367 ). for additional design information, see the application report designing with msp430 and segment lcd ( slaa654 ). 7.2.2.4 layout guidelines lcd segment (sx) and common (comx) signal traces are continuously switching while the lcd is enabled and should, therefore, be kept away from sensitive analog signals such as adc inputs to prevent any noise coupling. ti recommends keeping the lcd signal traces on one side of the pcb grouped together in a bus-like fashion. a ground plane underneath the lcd traces and guard traces employed alongside the lcd traces can provide shielding. if the internal charge pump of the lcd module is used, the externally provided capacitor on the lcdcap pin should be located as close as possible to the mcu. the capacitor should be connected to the device using a short and direct trace and also have a solid connection to the ground plane that is supplying the v ss pins of the mcu. for an example layout of connecting a 4-mux lcd with 40 segments to an msp430fr6989 and using the charge pump feature, see the gas or water meter with two lc sensors reference design ( tidm-lc- watermtr ). copyright ? 2014 ? 2015, texas instruments incorporated applications, implementation, and layout 155 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 7.2.3 extended scan interface (esi) peripheral 7.2.3.1 partial schematic the external connections for using the extended scan interface (esi) peripheral module depend on the esi operating mode and the application details. for example, using the esi in conjunction with analog lc sensors requires different connections than using the esi with resistive sensors. also, using optical sensors and encoders that have a digital output require different considerations. for reference implementations of using the esi to interface with different types of sensors to perform rotation detection, refer to the following table. these reference designs provide the hardware and software design files as well as analysis and user ? s guides to jumpstart your microcontroller-based projects. design name link gas or water meter with two lc sensors tidm-lc-watermtr mechanical-to-electronic converter with three lc sensors for gas or water meter tidm-3lc-meter-conv low-power flow meter design using giant magneto-resistive (gmr) sensors tidm-gmr-watermtr low-power flow meter design using optical sensors tidm-opticalwatermtr for schematic information related to other types of sensors and application use cases, refer to the "overview of extended scan interface applications" section in the extended scan interface (esi) chapter of the msp430fr58xx, msp430fr59xx, msp430fr68xx, and msp430fr69xx family user's guide ( slau367 ). 7.2.3.2 design requirements the hardware design requirements are specific to the use case and are most affected by the specification of the interaction of the chosen analog or digital sensors with the analog front ends (afe1 an afe2) of the esi. however, when designing the sensor circuit, the other digital parts of the esi module, namely the preprocessing unit (ppu), the processing state machine (psm) with its associated ram, the timing state machine (tsm), and the timer_a output stage must also be considered to ensure that the processing as required by the application can be performed in an autonomous manner inside the esi. refer to the extended scan interface (esi) chapter of the msp430fr58xx, msp430fr59xx, msp430fr68xx, and msp430fr69xx family user's guide ( slau367 ) for additional information regarding the design requirements and constraints of the module. 7.2.3.3 detailed design procedure ti provides a variety of collateral to aid the design and implementation of the esi into specific applications, most of which are related to metering. the following table gives an overview of the application notes that are currently available. additional application notes may be available in the device-specific product folder. literature document title no. lc sensor rotation detection with msp430 extended scan interface (esi) slaa639 method to select the value of lc sensor for msp430 extended scan interface (esi) slaa642 adjustment of esiosc oscillator frequency slaa609 migrating from msp430fw42x scan interface to msp430fr6x8x/fr5x8x extended scan interface slaa610 for complete and fully documented reference implementations that use the esi to interface with different types of sensors to perform rotation detection, refer to the table in section 7.2.3.1 . 156 applications, implementation, and layout copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 7.2.3.4 layout guidelines the proper operation of the esi and the connected sensor front end relies on a good analog board layout. specifically in case of using the esi analog front ends to interface with lc type or resistive sensors as typically employed in metering applications, the designer must make sure that the sensitive analog sensor signals are kept separated and guarded from any noise that might occur in the system including but not limited to the switching of lcd segment and common lines, communication signals, or any other type of digital i/o that is toggling. failure to follow proper precautions may reduce the sensitivity of the solution or may render the application inoperable. customers are encouraged to study and follow one of the available ti designs (see the table in section 7.2.3.1 ) for additional guidance. also see section 7.1.6 for more information that is applicable to this topic. copyright ? 2014 ? 2015, texas instruments incorporated applications, implementation, and layout 157 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 8 device and documentation support 8.1 device support 8.1.1 development tools support all msp430 ? microcontrollers are supported by a wide variety of software and hardware development tools. tools are available from ti and various third parties. see them all at www.ti.com/msp430tools . 8.1.1.1 hardware features see the code composer studio for msp430 user's guide ( slau157 ) for details on the available features. see the application reports advanced debugging using the enhanced emulation module (eem) with code composer studio version 6 ( slaa393 ) and msp430 ? advanced power optimizations: ulp advisor ? and energytrace ? technology ( slaa603 ) for further usage information. break- range lpmx.5 msp430 4-wire 2-wire clock state trace energy points break- debugging architecture jtag jtag control sequencer buffer trace++ (n) points support msp430xv2 yes yes 3 yes yes no no yes yes energytrace technology is supported with code composer studio version 6.0 and newer. it requires specialized debugger circuitry, which is supported with the second-generation on-board ez-fet flash emulation tool and second-generation standalone msp-fet jtag emulator. see the msp430 ? advanced power optimizations: ulp advisor ? and energytrace ? technology ( slaa603 ) application report, the code composer studio for msp430 user's guide ( slau157 ), and the msp430 hardware tools user's guide ( slau278 ) for more detailed information. 8.1.1.2 recommended hardware options 8.1.1.2.1 target socket boards the target socket boards allow easy programming and debugging of the device using jtag. they also feature header pin outs for prototyping. target socket boards are orderable individually or as a kit with the jtag programmer and debugger included. the following table shows the compatible target boards and the supported packages. see the msp430 hardware tools user's guide ( slau278 ) for board design information. package target board and programmer bundle target board only 100-pin lqfp (pz) msp-fet430u100d msp-ts430pz100d 8.1.1.2.2 experimenter boards experimenter boards and evaluation kits are available for some msp430 devices. these kits feature additional hardware components and connectivity for full system evaluation and prototyping. see www.ti.com/msp430tools for details. 8.1.1.2.3 debugging and programming tools hardware programming and debugging tools are available from ti and from its third-party suppliers. see the full list of available tools at www.ti.com/msp430tools . part number pc port features provider fast download and debugging. supports energytrace++ technology. msp-fet usb compatible with 4-wire jtag and 2-wire spy-bi-wire (sbw) jtag modes. texas instruments small form factor. legacy interface ? superseded by msp-fet. compatible with 4-wire jtag msp-fet430uif usb texas instruments and 2-wire spy-bi-wire (sbw) jtag modes. 158 device and documentation support copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 8.1.1.2.4 production programmers the production programmers expedite loading firmware to devices by programming several devices simultaneously. part number pc port features provider msp-gang serial and usb program up to eight devices at a time. works with pc or standalone. texas instruments 8.1.1.3 recommended software options 8.1.1.3.1 integrated development environments software development tools are available from ti or from third parties. open-source solutions are also available. see the full list of available tools at www.ti.com/msp430tools . this device is supported by the code composer studio ? ide (ccs) . see the msp debug stack (mspds) landing page ( www.ti.com/mspds ) for useful information about debugging tools. 8.1.1.3.2 msp430ware ? software msp430ware software is a collection of code examples, data sheets, and other design resources for all msp430 devices delivered in a convenient package. in addition to providing a complete collection of existing msp430 design resources, msp430ware software also includes a high-level api called msp430 driver library. this library makes it easy to program msp430 hardware. msp430ware software is available as a component of ccs or as a standalone package. 8.1.1.3.3 command-line programmer msp430 flasher is an open-source, shell-based interface for programming msp430 microcontrollers through a fet programmer or ez430 using jtag or spy-bi-wire (sbw) communication. msp430 flasher can be used to download binary files (.txt or .hex) files directly to the msp430 microcontroller without the need for an ide. 8.1.2 device and development tool nomenclature to designate the stages in the product development cycle, ti assigns prefixes to the part numbers of all msp430 mcu devices and support tools. each msp430 mcu commercial family member has one of three prefixes: msp, pms, or xms (for example, msp430fr69891). texas instruments recommends two of three possible prefix designators for its support tools: msp and mspx. these prefixes represent evolutionary stages of product development from engineering prototypes (with xms for devices and mspx for tools) through fully qualified production devices and tools (with msp for devices and msp for tools). device development evolutionary flow: xms ? experimental device that is not necessarily representative of the final device's electrical specifications pms ? final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification msp ? fully qualified production device support tool development evolutionary flow: mspx ? development-support product that has not yet completed texas instruments internal qualification testing. msp ? fully-qualified development-support product xms and pms devices and mspx development-support tools are shipped against the following disclaimer: copyright ? 2014 ? 2015, texas instruments incorporated device and documentation support 159 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com "developmental product is intended for internal evaluation purposes." msp devices and msp development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. ti's standard warranty applies. predictions show that prototype devices (xms and pms) have a greater failure rate than the standard production devices. texas instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. only qualified production devices are to be used. ti device nomenclature also includes a suffix with the device family name. this suffix indicates the package type (for example, pz) and temperature range (for example, i). figure 8-1 provides a legend for reading the complete device name for any family member. note: this figure does not represent a complete list of the available features and options, and does not indicate that all of these features and options are available for a given device or family. figure 8-1. device nomenclature ? part number decoder 160 device and documentation support copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887 processorfamily msp = mixed signal processor xms = experimental silicon 430 mcuplatform tis 16-bit low-power microcontroller platform device type memory type fr = fram series fram 6 series = up to 16 mhz with lcdfram 5 series = up to 16 mhz without lcd featureset first digit - aes 9 = aes 8 = no aes second digit - extended scan interface8 = esi 7 = no esi 2 = no esi, lcd, 64 pins third digit - fram (kb)9 = 128 8 = 96 7 = 64 6 = 48 optional fourth digit - bsl 1 = i c no value = uart 2 optional: temperature range packaging www.ti.com/packaging optional:distribution format optional: additional features -q1 = -ep = enhanced product (C40c to 105c) -ht = extreme temperature parts (C55c to 150c) automotive qualified t = small reel r = large reel no markings = tube or tray s = 0c to 50 c i = C40 c to 85 c t = C40 c to 105 c feature set series processor family optional: temperature range 430 mcu platform device type optional: distribution format packaging msp 430 fr 6 9891 i pz t optional: bsl fram aes esi
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 www.ti.com slase32a ? august 2014 ? revised march 2015 8.2 documentation support the following documents describe the msp430fr688x(1) and msp430fr588x(1) microcontrollers. copies of these documents are available on the internet at www.ti.com . slau367 msp430fr58xx, msp430fr59xx, msp430fr68xx, and msp430fr69xx family user's guide. detailed description of all modules and peripherals available in this device family. slaz521 msp430fr6889 device erratasheet. describes the known exceptions to the functional specifications for all silicon revisions of this device. slaz616 msp430fr68891 device erratasheet. describes the known exceptions to the functional specifications for all silicon revisions of this device. slaz531 msp430fr6888 device erratasheet. describes the known exceptions to the functional specifications for all silicon revisions of this device. slaz522 msp430fr6887 device erratasheet. describes the known exceptions to the functional specifications for all silicon revisions of this device. slaz527 msp430fr5889 device erratasheet. describes the known exceptions to the functional specifications for all silicon revisions of this device. slaz529 msp430fr58891 device erratasheet. describes the known exceptions to the functional specifications for all silicon revisions of this device. slaz528 msp430fr5888 device erratasheet. describes the known exceptions to the functional specifications for all silicon revisions of this device. slaz624 msp430fr5887 device erratasheet. describes the known exceptions to the functional specifications for all silicon revisions of this device. 8.2.1 related links table 8-1 lists quick access links. categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. table 8-1. related links technical tools & support & parts product folder sample & buy documents software community msp430fr6889 click here click here click here click here click here msp430fr68891 click here click here click here click here click here msp430fr6888 click here click here click here click here click here msp430fr6887 click here click here click here click here click here msp430fr5889 click here click here click here click here click here msp430fr58891 click here click here click here click here click here msp430fr5888 click here click here click here click here click here msp430fr5887 click here click here click here click here click here copyright ? 2014 ? 2015, texas instruments incorporated device and documentation support 161 submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
msp430fr6889 , msp430fr68891 , msp430fr6888 , msp430fr6887 msp430fr5889 , msp430fr58891 , msp430fr5888 , msp430fr5887 slase32a ? august 2014 ? revised march 2015 www.ti.com 8.2.2 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? community ti's engineer-to-engineer (e2e) community . created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers. ti embedded processors wiki texas instruments embedded processors wiki . established to help developers get started with embedded processors from texas instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices. 8.3 trademarks energytrace++, msp430, code composer studio, msp430ware, e2e are trademarks of texas instruments. microsoft is a registered trademark of microsoft corporation. all other trademarks are the property of their respective owners. 8.4 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 8.5 export control notice recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as defined by the u.s., eu, and other export administration regulations) including software, or any controlled product restricted by other applicable national regulations, received from disclosing party under nondisclosure obligations (if any), or any direct product of such technology, to any destination to which such export or re-export is restricted or prohibited by u.s. or other applicable laws, without obtaining prior authorization from u.s. department of commerce and other competent government authorities to the extent required by those laws. 8.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms and definitions. 9 mechanical, packaging, and orderable information 9.1 packaging information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. 162 mechanical, packaging, and orderable information copyright ? 2014 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430fr6889 msp430fr68891 msp430fr6888 msp430fr6887 msp430fr5889 msp430fr58891 msp430fr5888 msp430fr5887
package option addendum www.ti.com 12-jan-2015 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples msp430fr5887ipm active lqfp pm 64 160 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr5887 msp430fr5887ipmr active lqfp pm 64 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr5887 msp430fr5887irgcr active vqfn rgc 64 2000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr5887 msp430fr5887irgct active vqfn rgc 64 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr5887 msp430fr5888ipm active lqfp pm 64 160 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr5888 msp430fr5888ipmr active lqfp pm 64 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr5888 msp430fr5888irgcr active vqfn rgc 64 2000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr5888 msp430fr5888irgct active vqfn rgc 64 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr5888 msp430fr58891ipm active lqfp pm 64 160 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr58891 msp430fr58891ipmr active lqfp pm 64 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr58891 msp430fr58891irgcr active vqfn rgc 64 2000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr58891 msp430fr58891irgct active vqfn rgc 64 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr58891 msp430fr5889ipm active lqfp pm 64 160 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr5889 msp430fr5889ipmr active lqfp pm 64 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr5889 msp430fr5889irgcr active vqfn rgc 64 2000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr5889 msp430fr5889irgct active vqfn rgc 64 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr5889 msp430fr6887ipn active lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr6887
package option addendum www.ti.com 12-jan-2015 addendum-page 2 orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples msp430fr6887ipnr active lqfp pn 80 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr6887 msp430fr6887ipz active lqfp pz 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr6887 msp430fr6887ipzr active lqfp pz 100 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr6887 msp430fr6888ipn active lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr6888 MSP430FR6888IPNR active lqfp pn 80 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr6888 msp430fr6888ipz active lqfp pz 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr6888 msp430fr6888ipzr active lqfp pz 100 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr6888 msp430fr68891ipn active lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr68891 msp430fr68891ipnr active lqfp pn 80 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr fr68891 msp430fr68891ipz active lqfp pz 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr68891 msp430fr68891ipzr active lqfp pz 100 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr68891 msp430fr6889ipn active lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr6889 msp430fr6889ipnr active lqfp pn 80 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr6889 msp430fr6889ipz active lqfp pz 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr6889 msp430fr6889ipzr active lqfp pz 100 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr6889 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device.
package option addendum www.ti.com 12-jan-2015 addendum-page 3 (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant msp430fr5887ipmr lqfp pm 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 q2 msp430fr5887irgcr vqfn rgc 64 2000 330.0 16.4 9.3 9.3 1.1 12.0 16.0 q2 msp430fr5887irgct vqfn rgc 64 250 180.0 16.4 9.3 9.3 1.1 12.0 16.0 q2 msp430fr5888ipmr lqfp pm 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 q2 msp430fr5888irgcr vqfn rgc 64 2000 330.0 16.4 9.3 9.3 1.1 12.0 16.0 q2 msp430fr5888irgct vqfn rgc 64 250 180.0 16.4 9.3 9.3 1.1 12.0 16.0 q2 msp430fr58891ipmr lqfp pm 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 q2 msp430fr58891irgcr vqfn rgc 64 2000 330.0 16.4 9.3 9.3 1.1 12.0 16.0 q2 msp430fr58891irgct vqfn rgc 64 250 180.0 16.4 9.3 9.3 1.1 12.0 16.0 q2 msp430fr5889ipmr lqfp pm 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 q2 msp430fr5889irgcr vqfn rgc 64 2000 330.0 16.4 9.3 9.3 1.1 12.0 16.0 q2 msp430fr5889irgct vqfn rgc 64 250 180.0 16.4 9.3 9.3 1.1 12.0 16.0 q2 msp430fr6887ipnr lqfp pn 80 1000 330.0 24.4 15.0 15.0 2.1 20.0 24.0 q2 msp430fr6887ipzr lqfp pz 100 1000 330.0 24.4 17.0 17.0 2.1 20.0 24.0 q2 MSP430FR6888IPNR lqfp pn 80 1000 330.0 24.4 15.0 15.0 2.1 20.0 24.0 q2 msp430fr6888ipzr lqfp pz 100 1000 330.0 24.4 17.0 17.0 2.1 20.0 24.0 q2 msp430fr68891ipnr lqfp pn 80 1000 330.0 24.4 15.0 15.0 2.1 20.0 24.0 q2 msp430fr68891ipzr lqfp pz 100 1000 330.0 24.4 17.0 17.0 2.1 20.0 24.0 q2 package materials information www.ti.com 11-apr-2015 pack materials-page 1
device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant msp430fr6889ipnr lqfp pn 80 1000 330.0 24.4 15.0 15.0 2.1 20.0 24.0 q2 msp430fr6889ipzr lqfp pz 100 1000 330.0 24.4 17.0 17.0 2.1 20.0 24.0 q2 *all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) msp430fr5887ipmr lqfp pm 64 1000 367.0 367.0 45.0 msp430fr5887irgcr vqfn rgc 64 2000 367.0 367.0 38.0 msp430fr5887irgct vqfn rgc 64 250 210.0 185.0 35.0 msp430fr5888ipmr lqfp pm 64 1000 367.0 367.0 45.0 msp430fr5888irgcr vqfn rgc 64 2000 367.0 367.0 38.0 msp430fr5888irgct vqfn rgc 64 250 210.0 185.0 35.0 msp430fr58891ipmr lqfp pm 64 1000 367.0 367.0 45.0 msp430fr58891irgcr vqfn rgc 64 2000 367.0 367.0 38.0 msp430fr58891irgct vqfn rgc 64 250 210.0 185.0 35.0 msp430fr5889ipmr lqfp pm 64 1000 367.0 367.0 45.0 msp430fr5889irgcr vqfn rgc 64 2000 367.0 367.0 38.0 msp430fr5889irgct vqfn rgc 64 250 210.0 185.0 35.0 msp430fr6887ipnr lqfp pn 80 1000 367.0 367.0 45.0 msp430fr6887ipzr lqfp pz 100 1000 367.0 367.0 45.0 MSP430FR6888IPNR lqfp pn 80 1000 367.0 367.0 45.0 package materials information www.ti.com 11-apr-2015 pack materials-page 2
device package type package drawing pins spq length (mm) width (mm) height (mm) msp430fr6888ipzr lqfp pz 100 1000 367.0 367.0 45.0 msp430fr68891ipnr lqfp pn 80 1000 367.0 367.0 45.0 msp430fr68891ipzr lqfp pz 100 1000 367.0 367.0 45.0 msp430fr6889ipnr lqfp pn 80 1000 367.0 367.0 45.0 msp430fr6889ipzr lqfp pz 100 1000 367.0 367.0 45.0 package materials information www.ti.com 11-apr-2015 pack materials-page 3

mechanical data mtqf008a january 1995 revised december 1996 1 post office box 655303 ? dallas, texas 75265 pm (s-pqfp-g64) plastic quad flatpack 4040152 / c 11/96 32 17 0,13 nom 0,25 0,45 0,75 seating plane 0,05 min gage plane 0,27 33 16 48 1 0,17 49 64 sq sq 10,20 11,80 12,20 9,80 7,50 typ 1,60 max 1,45 1,35 0,08 0,50 m 0,08 0 7 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026 d. may also be thermally enhanced plastic with leads connected to the die pads.

mechanical data mtqf010a january 1995 revised december 1996 1 post office box 655303 ? dallas, texas 75265 pn (s-pqfp-g80) plastic quad flatpack 4040135 / b 11/96 0,17 0,27 0,13 nom 40 21 0,25 0,45 0,75 0,05 min seating plane gage plane 41 60 61 80 20 sq sq 1 13,80 14,20 12,20 9,50 typ 11,80 1,45 1,35 1,60 max 0,08 0,50 m 0,08 0 7 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026
mechanical data mtqf013a october 1994 revised december 1996 1 post office box 655303 ? dallas, texas 75265 pz (s-pqfp-g100) plastic quad flatpack 4040149 /b 11/96 50 26 0,13 nom gage plane 0,25 0,45 0,75 0,05 min 0,27 51 25 75 1 12,00 typ 0,17 76 100 sq sq 15,80 16,20 13,80 1,35 1,45 1,60 max 14,20 0 7 seating plane 0,08 0,50 m 0,08 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026
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